ST72372J4T1 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72372J4T1

8-BIT MCUs WITH 16K ROM/OTP/EPROM, 512 BYTES RAM, ADC, DAC (PWM), TIMER, I2C AND SCI

STMicroelectronics 

ST72371/ST72372

16-BIT TIMER (Cont’d)

4.3.3.7 Pulse Width Modulation Mode

Pulse Width Modulation mode enables the gener-

ation of a signal with a frequency and pulse length

determined by the value of the OC1R and OC2R

registers.

The pulse width modulation mode uses the com-

plete Output Compare 1 function plus the OC2R

register.

Procedure

To use pulse width modulation mode:

1. Load the OC2R register with the value corre-

sponding to the period of the signal.

2. Load the OC1R register with the value corre-

sponding to the length of the pulse if (OLVL1=0

and OLVL2=1).

3. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with OC1R register.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with OC2R register.

4. Select the following in the CR2 register:

– Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function.

– Set the PWM bit.

– Select the timer clock (CC1-CC0) (seeTable

1).

If OLVL1=1 and OLVL2=0 the length of the pulse

is the difference between the OC2R and OC1R

registers.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

OCiR Value =

t * fCPU - 5

tPRESC

Where:

– t = Desired output compare period (seconds)

– fCPU = Internal clock frequency (see Miscella-

neous register)

– tPRESC = Timer clock prescaler (CC1-CC0

bits , see Table 1)

The Output Compare 2 event causes the counter

to be initialized to FFFCh (SeeFigure 10).

Pulse Width Modulation cycle

When

Counter

= OC1R

OCMP1 = OLVL1

When

Counter

= OC2R

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

Note: After a write instruction to the OCiHR regis-

ter, the output compare function is inhibited until

the OCiLR register is also written.

The ICF1 bit is set by hardware when the counter

reaches the OC2R value and can produce a timer

interrupt if the ICIE bit is set and the I bit is cleared.

Therefore the Input Capture 1 function is inhibited

but the Input Capture 2 is available.

The OCF1 and OCF2 bits cannot be set by hard-

ware in PWM mode therefore the Output Compare

interrupt is inhibited.

When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

Figure 26. Pulse Width Modulation Mode Timing

COUNTER 34E2 FFFC FFFD FFFE

OCMP1

compare2

OLVL2

2ED0 2ED1 2ED2 34E2 FFFC

OLVL1

compare1

OLVL2

compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

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