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ST72F521R9TC View Datasheet(PDF) - STMicroelectronics

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ST72F521R9TC Datasheet PDF : 211 Pages
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ST72521
CONTROLLER AREA NETWORK (Cont’d)
10.8.5 List of CAN Cell Limitations
10.8.5.1 Omitted SOF bit
Symptom:
Start of Frame (SOF) bit is omitted if transmission
is requested in the last Intermission bit.
Test Case:
5.3.1 10-Kbit Stress Test
Details:
The IUT is requested to start transmission immedi-
ately after the completion of the previous transmis-
sion. The LT also starts its transmission and as-
serts the SOF bit just after the 3rd Intermission bit.
The IUT also starts transmission but omits the
SOF bit. The IUT wins the arbitration and contin-
ues the transmission. The frame is sent correctly.
Impact On The Application:
As this effect only occurs when the IUT detects a
SOF bit on the CAN bus, the fact that it omits its
own SOF bit has no impact on the communication.
10.8.5.2 CAN: CPU Write Access (More Than
One Cycle) Corrupts CAN Frame
Symptoms:
For CAN received messages the identifier high
byte or last data byte can be corrupted.
For CAN transmitted messages the 2nd data byte
can be corrupted.
Details:
The CAN transmit and receive buffers are imple-
mented as dual ported RAM. During the reception
of a CAN frame the CAN core writes the received
identifier and the data byte-by-byte in the corre-
sponding buffer.
IF the CAN bit timing configuration is tBS2 < 5 time
quanta
AND
IF concurrently with the pCAN, the CPU executes
a write access to the dual ported RAM using an in-
struction with more than one cycle access, e.g.
CLR, BSET, BRES
THEN the access conflict can lead to the corrup-
tion described in the symptoms paragraph above.
Impact On The Application:
Several CAN frames with erroneous data or iden-
tifier will be received/transmitted.
Software Workaround:
Program tBS2 > 4 time quanta or, when accessing
the receive or transmit buffers, do not use the crit-
ical instructions which are:
BSET, BRES, CLR, CPL, DEC, INC, NEG, RLC,
SLL, SRL, RRC, SRA, SWAP.
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