ST72521AR9TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72521AR9TC

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

STMicroelectronics 

ST72521

15 IMPORTANT NOTES

15.1 Silicon Identification

This section refers to ST72F521/ST72521 devices

shown in Table 31 and Table 32. They are identifi-

able both by the last letter of the Trace code

marked on the device package and by the last 3

digits of the Internal Sales Type printed on the

box label.

Table 31. Flash Device Identification

Part

Number

ST72F521

xxxx

ST72F521

xxxx

ST72F521

xxxx

Trace Code

marked on device

“xxxxxxxxxQ”

(current revision)

“xxxxxxxxxR”

“xxxxxxxxxS”

Internal Sales Type

on box label

72F521xxxx$A2

72F521xxxx$U2

72F521xxxx$A9

72F521xxxx$U9

72F521xxxx$U8

Table 32. ROM Device Identification

Part

Number

ST72521x

xxx

Trace Code

marked on device

“xxxxxxxxxW”

Internal Sales Type

on box label

72521xxxx/xxx$D5

72521xxxx/xxx$U5

15.2 ALL FLASH AND ROM DEVICES

15.2.1 External RC option

The External RC clock source option described in

previous datasheet revisions is no longer support-

ed and has been removed from this specification.

15.2.2 CSS Function

The Clock Security System function is not guaran-

teed. The features described in Section 6.4.3 are

subject to revision.

15.2.3 Safe Connection of OSC1/OSC2 Pins

The OSC1 and/or OSC2 pins must not be left un-

connected otherwise the ST7 main oscillator may

start and, in this configuration, could generate an

fOSC clock frequency in excess of the allowed

maximum (>16MHz.), putting the ST7 in an un-

safe/undefined state. Refer to Section 6.2 on page

25.

15.2.4 Unexpected Reset Fetch

If an interrupt request occurs while a "POP CC" in-

struction is executed, the interrupt controller does

not recognise the source of the interrupt and, by

default, passes the RESET vector address to the

CPU.

Workaround

To solve this issue, a "POP CC" instruction must

always be preceded by a "SIM" instruction.

15.2.5 Internal RC Oscillator with LVD

The internal RC can only be used if LVD is ena-

bled.

15.2.6 Read-out protection with LVD

The LVD is not supported if the read-out protection

is enabled.

15.2.7 16-bit Timer PWM Mode

In PWM mode, the first PWM pulse is missed after

writing the value FFFCh in the OC1R register

(OC1HR, OC1LR). It leads to either full or no PWM

during a period, depending on the OLVL1 and

OLVL2 settings.

15.2.8 I/O behaviour during ICC mode entry

sequence

Symptom

In 80-pin devices (Flash), both Port G and H are

forced to output push-pull during ICC mode entry

sequence. 80-pin ROM devices are not impacted

by this issue.

Details

206/211

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