ST7PMC2S7B6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7PMC2S7B6

8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI™

STMicroelectronics 

ST7MC1xx/ST7MC2xx

MOTOR CONTROLLER (Cont’d)

AN WEIGHT REGISTER (MWGHT)

Read/Write

Reset Value: 0000 0000 (00h)

7

6

5

4

3

2

1

0

AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0

Bits 7:0 = AN[7:0]: A Weight Value.

These bits contain the AN weight value for the mul-

tiplier. In autoswitched mode the MCOMP register

is automatically loaded with:

Zn x MWGHT or ZN-1 x MWGHT (*)

256(d)

256(d)

when a Z event occurs.

(*) depending on the DCB bit in the MCRA regis-

ter.

PRESCALER & SAMPLING REGISTER

(MPRSR)

Read/Write

Reset Value: 0000 0000 (00h)

7

6

5

4

3

2

1

0

SA3 SA2 SA1 SA0 ST3 ST2 ST1 ST0

Bits 7:4 = SA[3:0]: Sampling Ratio.

These bits contain the sampling ratio value for cur-

rent mode. Refer to Table 47, “Sampling Frequen-

cy Selection,” on page 189.

Bits 3:0 = ST[3:0]: Step Ratio.

These bits contain the step ratio value. It acts as a

prescaler for the MTIM timer and is auto incre-

mented/decremented with each R+ or R- event.

Refer to Table 40, “Step Frequency/Period Range

(4MHz),” on page 179 and Table 41, “Modes of

Accessing MTIM Timer-Related Registers,” on

page 179.

INTERRUPT MASK REGISTER (MIMR)

Read/Write

Reset Value: 0000 0000 (00h)

7

6

5

4

3

2

1

0

PUM SEM RIM CLIM EIM ZIM DIM CIM

Bit 7 = PUM: PWM Update Mask bit.

0: PWM Update interrupt disabled

1: PWM Update interrupt enabled

Bit 6 = SEM: Speed Error Mask bit.

0: Speed Error interrupt disabled

1: Speed Error interrupt enabled

Bit 5 = RIM: Ratio update Interrupt Mask bit.

0: Ratio update interrupts (R+ and R-) disabled

1: Ratio update interrupts (R+ and R-) enabled

Bit 4 = CLIM: Current Limitation Interrupt Mask bit.

0: Current Limitation interrupt disabled

1: Current Limitation interrupt enabled

This interrupt is available only in Voltage Mode

(VOC1 bit=0 in MCRA register) and occurs when

the Motor current feedback reaches the external

current limitation value.

Bit 3 = EIM: Emergency stop Interrupt Mask bit.

0: Emergency stop interrupt disabled

1: Emergency stop interrupt enabled

Bit 2 = ZIM: Back EMF Zero-crossing Interrupt

Mask bit.

0: BEMF Zero-crossing Interrupt disabled

1: BEMF Zero-crossing Interrupt enabled

Bit 1 = DIM: End of Demagnetization Interrupt

Mask bit.

0: End of Demagnetization interrupt disabled

1: End of Demagnetization interrupt enabled if the

HDM or SDM bit in the MCRB register is set

Bit 0 = CIM: Commutation / Capture Interrupt

Mask bit

0: Commutation / Capture Interrupt disabled

1: Commutation / Capture Interrupt enabled

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