ST7MC2N6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7MC2N6

8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI™

STMicroelectronics 

ST7MC1xx/ST7MC2xx

INSTRUCTION SET OVERVIEW (Cont’d)

11.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set

consisting of 63 instructions. The instructions may

be subdivided into 13 main groups as illustrated in

the following table:

Load and Transfer

Stack operation

Increment/Decrement

Compare and Tests

Logical operations

Bit Operation

Conditional Bit Test and Branch

Arithmetic operations

Shift and Rotates

Unconditional Jump or Call

Conditional Branch

Interruption management

Condition Code Flag modification

LD

PUSH

INC

CP

AND

BSET

BTJT

ADC

SLL

JRA

JRxx

TRAP

SIM

CLR

POP

DEC

TNZ

OR

BRES

BTJF

ADD

SRL

JRT

WFI

RIM

RSP

BCP

XOR

SUB

SRA

JRF

HALT

SCF

CPL NEG

SBC

RLC

JP

MUL

RRC

CALL

SWAP

CALLR

IRET

RCF

SLA

NOP RET

Using a pre-byte

The instructions are described with one to four op-

codes.

In order to extend the number of available op-

codes for an 8-bit CPU (256 opcodes), three differ-

ent prebyte opcodes are defined. These prebytes

modify the meaning of the instruction they pre-

cede.

The whole instruction becomes:

PC-2

End of previous instruction

PC-1

Prebyte

PC

opcode

PC+1

Additional word (0 to 2) according

to the number of bytes required to compute the ef-

fective address

These prebytes enable instruction in Y as well as

indirect addressing modes to be implemented.

They precede the opcode of the instruction in X or

the instruction using direct addressing mode. The

prebytes are:

PDY 90

Replace an X based instruction

using immediate, direct, indexed, or inherent ad-

dressing mode by a Y one.

PIX 92

Replace an instruction using di-

rect, direct bit, or direct relative addressing mode

to an instruction using the corresponding indirect

addressing mode.

It also changes an instruction using X indexed ad-

dressing mode to an instruction using indirect X in-

dexed addressing mode.

PIY 91

Replace an instruction using X in-

direct indexed addressing mode by a Y one.

11.2.1 Illegal Opcode Reset

In order to provide enhanced robustness to the de-

vice against unexpected behaviour, a system of il-

legal opcode detection is implemented. If a code to

be executed does not correspond to any opcode

or prebyte value, a reset is generated. This, com-

bined with the Watchdog, allows the detection and

recovery from an unexpected fault or interference.

Note: A valid prebyte associated with a valid op-

code forming an unauthorized combination does

not generate a reset.

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