ST7FMC1M2T3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7FMC1M2T3

8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI™

STMicroelectronics 

ST7MC1xx/ST7MC2xx

16-BIT TIMER (Cont’d)

Notes:

1. After a processor write cycle to the OCiHR reg-

ister, the output compare function is inhibited

until the OCiLR register is also written.

2. If the OCiE bit is not set, the OCMPi pin is a

general I/O port and the OLVLi bit will not

appear when a match is found but an interrupt

could be generated if the OCIE bit is set.

3. In both internal and external clock modes, OCFi

and OCMPi are set while the counter value

equals the OCiR register value (see Figure 51

for an example with fCPU/2 and Figure 52 for an

example with fCPU/4). This behavior is the same

in OPM or PWM mode.

4. The output compare functions can be used both

for generating external events on the OCMPi

pins even if the input capture mode is also

used.

5. The value in the 16-bit OCiR register and the

OLVi bit should be changed after each suc-

cessful comparison in order to control an output

waveform or establish a new elapsed timeout.

Forced Compare Output capability

When the FOLVi bit is set by software, the OLVLi

bit is copied to the OCMPi pin. The OLVi bit has to

be toggled in order to toggle the OCMPi pin when

it is enabled (OCiE bit=1). The OCFi bit is then not

set by hardware, and thus no interrupt request is

generated.

FOLVLi bits have no effect in both one pulse mode

and PWM mode.

Figure 50. Output Compare Block Diagram

16 BIT FREE RUNNING

COUNTER

16-bit

OUTPUT COMPARE

CIRCUIT

16-bit

16-bit

OC1R Register

OC2R Register

OC1E OC2E

OCIE

CC1 CC0

(Control Register 2) CR2

(Control Register 1) CR1

FOLV2 FOLV1 OLVL2

OLVL1

OCF1

OCF2 0

0

0

(Status Register) SR

Latch

1

Latch

2

OCMP1

Pin

OCMP2

Pin

83/309

1

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