ST92195C/D - INTERRUPTS
EXTERNAL INTERRUPTS (Cont’d)
Figure 26. External Interrupts Control Bits and Vectors
n
Watchdog/Timer IA0S
End of count
TEA0
“0”
VECTOR V7 V6 V5 V4 0 0 0 0
Priority level PL2A PL1A 0
INT 0 pin
“1”
* INTS0
Mask bit IMA0
Pending bit IPA0
INT A0
request
INT 2 pin
INT 4 pin
INT 5 pin
INT 6 pin
Std. Timer 0
“0”
Not connected
“1”
TEB0
SPEN,BMS
SPI Interrupt
“1,x”
“0,0”
*
CLEAR
I²C
ADINT
TEC0
EOFVBI
(SYNC inter)
“0”
“1”
VBEN
“1”
“0”
TEC1
FLDST
(SYNC inter)
FSTEN
“1”
“0”
INTS1
Std. Timer 1
“0”
“1”
VECTOR V7 V6 V5 V4 0 0 1 0
Priority level PL2A PL1A 1
Mask bit IMA1
Pending bit IPA1
INT A1
request
VECTOR V7 V6 V5 V4 0 1 0 0
Priority level PL2B PL1B 0
Mask bit IMB0
Pending bit IPB0
INT B0
request
VECTOR V7 V6 V5 V4 0 1 1 0
Priority level PL2B PL1B 1
Mask bit IMB1
Pending bit IPB1
INT B1
request
VECTOR V7 V6 V5 V4 1 0 0 0
Priority level PL2C PL1C 0
Mask bit IMC0
Pending bit IPC0
INT C0
request
TED0
VECTOR V7 V6 V5 V4 1 0 1 0
Priority level PL2C PL1C 1
Mask bit IMC1
Pending bit IPC1
TED1
VECTOR V7 V6 V5 V4 1 1 0 0
Priority level PL2D PL1D 0
Mask bit IMD0
Pending bit IPD0
INT C1
request
INT D0
request
INT 7 pin
VECTOR V7 V6 V5 V4 1 1 1 0
Priority level PL2D PL1D 1
Mask bit IMD1
Pending bit IPD1
INT D1
request
* Shared channels, see warning
n
53/249