ST92195C/D - TELETEXT DISPLAY STORAGE RAM INTERFACE
TDSRAM (Cont’d)
Figure 48. Timesharing Slot Configurations
Deflection line 1
DIS
DIS
CPU
CPU
CPU
CPU
CPU
CPU
MBT
CPU
MBT
CPU
ACQ
ACQ
ACQ
ACQ
DIS
DIS
CPU
CPU
CPU
CPU
CPU
CPU
MBT
CPU
MBT
CPU
CPU
CPU
CPU
CPU
DON = 1 or AON =1, BUSY = 1
DON = 1 or AON =1, BUSY = 0
DON = 0 or AON =1, BUSY = 1
DON = 0 or AON =1, BUSY = 0
B
CVBS
TXT
U
Acquisition F 41
Data
unit
F Bytes
Slicer
E
R
ACCESS cycle
MBT
40 bytes
ACCESS cycle
ACCESS cycle
PPaP2agagteogee8k
memory
ST9 CPU
AACCCCEESSSSccyyccllee
WAIT~
Bus register
TRI
TDS RAM
Interface
Font
ROM
ACCESS cycle
DSI
On Screen
Display
R
G
B
BLANK
VR02112D
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