ST92T195 View Datasheet(PDF) - STMicroelectronics
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ST92T195 Datasheet PDF : 249 Pages
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ST92195C/D - TELETEXT DISPLAY STORAGE RAM INTERFACE
TDSRAM (Cont’d)
7.3.2.3 CPU Slowdown on TDSRAM access
As described above, the TDSRAM interface puts
priority on TV real time constraints and may slow-
down the CPU by inserting wait cycles when a TD-
SRAM access is requested. The effective duration
of the CPU slowdown is a complex function of TD-
SRAM interface working mode and of the respec-
tive DOTCK/2 frequency (TDSRAM frequency)
and the Core INTCLK frequency.
In order to calculate the average and worst case
slowdown, let’s define the following parameters:
INT(): stands for "integer" function
TCPU: CPU internal clock period
TDRAM: TDSRAM clock period (DOTCLK/2 peri-
od)
TWAIT: additional time inserted due to the TD-
SRAM access
S: number of elapsed slots to get a CPU slot (this
may be a real number)
TWAIT (read) = INT(2.5 * S * (TDRAM/ TCPU)) *
TCPU + (+1 / -0) * TCPU
TWAIT (write) = INT(2.5 * S * (TDRAM/ TCPU) +
1) * TCPU + (+1 / -0) * TCPU
DIS (or ACQ) slot
off
off
on
on
MBT slot
on
off
off
on
Average S
12/8 = 1.5
9/8 = 1.16
12/8 = 1.5
16/8 = 2
Max S
3
2
3
4
Assuming the Display is "on", no "MBT" is required
and we have the following clock conditions:
CPU running at 12 MHz (TCPU= 83ns)
DOTCK/2 at 20 MHz; 4/3 recommended frequen-
cy (TDRAM= 50ns) the average number of insert-
ed wait cycles is:
TWAIT(read) = 2 * TCPU + (+1 / -0) * TCPU
(i.e. 2 or 3 extra CPU cycles)
TWAIT(write) = 3 * TCPU + (+1 / -0) * TCPU
(i.e. 3 or 4 extra CPU cycles)
In practice:
ld (rr), #N will last 11 or 12 cycles instead
of 8 cycles
ldw (rr), #NN will last 20 to 22 cycles instead
of 14 cycles
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