ST92196A REGISTER MAP (Cont’d)
Table 7. Detailed Register Map
Group F
Page
Dec.
N/A
0
2
Block
I/O
Port
0:5
Core
INT
WDT
SPI
I/O
Port
0
I/O
Port
2
I/O
Port
3
Reg.
No.
R224
R226
R227
R228
R229
R230
R231
R232
R233
R234
R235
R236
R237
R238
R239
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R240
R241
R242
R248
R249
R250
R252
R253
R254
Register
Name
P0DR
P2DR
P3DR
P4DR
P5DR
CICR
FLAGR
RP0
RP1
PPR
MODER
USPHR
USPLR
SSPHR
SSPLR
EITR
EIPR
EIMR
EIPLR
EIVR
NICR
WDTHR
WDTLR
WDTPR
WDTCR
WCR
SPIDR
SPICR
P0C0
P0C1
P0C2
P2C0
P2C1
P2C2
P3C0
P3C1
P3C2
GENERAL DESCRIPTION
Description
Port 0 Data Register
Port 2 Data Register
Port 3 Data Register
Port 4 Data Register
Port 5 Data Register
Central Interrupt Control Register
Flag Register
Pointer 0 Register
Pointer 1 Register
Page Pointer Register
Mode Register
User Stack Pointer High Register
User Stack Pointer Low Register
System Stack Pointer High Reg.
System Stack Pointer Low Reg.
External Interrupt Trigger Register
External Interrupt Pending Reg.
External Interrupt Mask-bit Reg.
External Interrupt Priority Level Reg.
External Interrupt Vector Register
Nested Interrupt Control
Watchdog Timer High Register
Watchdog Timer Low Register
Watchdog Timer Prescaler Reg.
Watchdog Timer Control Register
Wait Control Register
SPI Data Register
SPI Control Register
Port 0 Configuration Register 0
Port 0 Configuration Register 1
Port 0 Configuration Register 2
Port 2 Configuration Register 0
Port 2 Configuration Register 1
Port 2 Configuration Register 2
Port 3 Configuration Register 0
Port 3 Configuration Register 1
Port 3 Configuration Register 2
Reset
Value
Hex.
Doc.
Page
FF
FF
FF 69
FF
FF
87
27
00
28
00
30
00
30
54
32
E0 32
xx
34
xx
34
xx
34
xx
34
00
56
00
56
00
56
FF 57
x6
57
00
57
FF 81
FF 81
FF 81
12
81
7F
82
xx 190
00 190
00
00
00
00
00
69
00
00
00
00
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