STA321TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA321TR Datasheet PDF : 157 Pages
| |||
STA321
Clock management
5.2
Peripheral clock manager
This block manages the clocks of the core processing peripherals ADC, FFX, PROC
(including memories and SAI interfaces) and SRC.
A clock divider (by 2) is attached before every block except the FFX.
Each block is attached to a global gating cell and to a dedicated one. This allows a flexible
power-consumption management because it is possible to turn off either the whole
processing chain or just a single block. The only exception is the I2C peripheral clock which
is disabled only when the device is in hardware power-down mode. In all the other cases this
clock remains active.
5.3
Fractional PLL
The PLL specifications are given in Table 6 on page 14.
Figure 12. PLL block diagram
PLL_CLK_in
pll_clk_in
CLCKLINKIN
PLLCPFLLGC0F[3G:00(]3-0) IIDDFF
PPLLLL__PPWWDDNN
PLLCFGP3L[L7C]FG3(7) PLL_SplTl_RstBrb
PLLCFGP3L[L6C]FGP3L(6L)_STplRl_BstBrbYbPyp
PLLCFGPL0L[6C]FGP0L(6L)_FRp_lCl_fTr_RcLtrl
IDF
Input freq. divider
Lock detect
F_INT
Buffer
PFD
LPF
cpump
VCO
LDF
Loop freq. divider
Fractional
controller
LLOOCCKKPP
FVVCCOO
5.3.1
DITHER
DITDHisEaRble
FRAC
FIRnpAuCt
NNDDIIVV
PDLLisCaFbGle0(5-4)
PLLCFG0[5:4]
PPLLLLCCIPnFFLpGGLu12Ct((77F--G00))1[7:P0L]LCPFLGL3C(5F-0G) 3[5:0]
PLLCFG2[7:0]
PLL block description
Phase/frequency detector (PFD)
This block compares the phase difference between the corresponding rising edges of the
F_INT and the clock coming from the loop frequency divider.
It generates voltage pulses with widths proportional to the input phase error.
Charge pump and loop filter (LPF/CPUMP)
This block converts the voltage pulses from the phase/frequency detector to current pulses
which charge the loop filter and generate the control voltage for the voltage controlled
oscillator (VCO).
Doc ID 15351 Rev 3
31/157
Share Link: 