STA321TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STA321TR

4-channel digital audio system with FFX™ driver

STMicroelectronics 

STA321

Power-up and power-down sequences

Table 9. Startup timings

Parameter

Description

DC reg. power-up time

Start up time of the DC Regulator after

connecting the power

Device in reset mode

Must be greater than

(VDD time + DC reg. power-up time)

Min Typ Max Unit

-

-

300 µs

-

-

-

µs

Table 10. Configuration example

Register

address

Value

Description

0xC9

0xCA

0x00

0x00

Remove PLL bypass

Headphone detection polarity = 0

0xB8

0xB7

0xC6

0xB2

0x4A

0x38

0x02

0xF3

Configure SAI output: SAI_out1 = SAI_in1, SAI_out2 = SAI_in2

SRC source select: SRC1 = ADC, SRC2 = ADC

ADC clock on

I2S configuration

0xC8

0xB2

0xA0

0x00

0x21

0xD3

0x00

0x00

Core clock on, SAI/ADC audio set to 32 kHz - 48 kHz range

SAI_out: output enabled

Soft volume removed

Remove bridge 3-state

4.2

Software power-down mode

The software power-down is obtained by configuring the appropriate I2C registers.

In order to obtain flexibility every peripheral has its independent, standby signal and several

gating clock cells are available.

Obviously, the I2C peripheral can not be turned off in this mode, otherwise the device can

recover from the power-down state only via the reset pin.

In the table below EA is embedded amplifier and CB is CMOS bridge. For complete

information this table must be used in conjunction with Chapter 14: Register description on

page 77.

Table 11. Registers for power-down

Description

Put EA in standby

Put CB in standby

Put PLL in standby

Put ADC in standby

Turn core clock off

Turn ADC clock off

Register bit

FFXCFG1[7]

FFXCFG1[6]

PLLPFE[5]

ADCCFG0[3]

MISC[0]

ADCCFG0[1]

Address

0x00 on page 81

0x00

0xC4 on page 132

0xC6 on page 133

0xC8 on page 135

0xC6

Doc ID 15351 Rev 3

21/157

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