Power-up and power-down sequences
Table 13. Frequently used signals
Name
Description
STBY
PWDN
DC regulator
A. OK
DC regulator
CMP_EN_N
EA_STBY
CB_STBY
EA/CB volume
PLL_UNLOCK
PLL_PWDN
CLK_PROC_ON
CLK_PROC
CLK_FFX_ON
clk_ffx
CLK_ADC_ON
clk_adc
CLK_SRC_ON
clk_src
CMP_EN_N
DC_STBY_EN
FFX_ULCK_PLL
Input pin STBY on page 11
Internal
Internal
Bit 1, register STBY_MODES on page 139
Bits 7:6, register FFXCFG1 on page 81
Internal
Bit 7, register PLLST on page 132
Bit 5, register PLLPFE on page 132
Bit 2, register CKOCFG on page 134
Processing clock
Bit 4, register CKOCFG on page 134
FFX clock
Bit 1, register ADCCFG0 on page 133
ADC clock
Bit 3, register CKOCFG on page 134
SRC clock
Bit 1, register STBY_MODES on page 139
Bit 0, register STBY_MODES on page 139
Bits 4:3, register FFXCFG1 on page 81
STA321
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Doc ID 15351 Rev 3