STA321TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STA321TR

4-channel digital audio system with FFX™ driver

STMicroelectronics 

Power-up and power-down sequences

STA321

4.2.1

Note:

Table 11. Registers for power-down (continued)

Description

Register bit

Turn SRC clock off

CKOCFG[3]

Turn PROC clock off

CKOCFG[2]

Turn FFX clock off

CKOCFG[4]

Address

0xC7 on page 134

0xC7

0xC7

Configuration example

This is an example of the register setup for power-down clock. It is assumed that every

peripheral is already configured and working correctly.

There are other configuration examples to help you get started please refer to other

chapters and also to Chapter 14: Register description on page 77 in order to get all the

necessary and complementary details.

Turn off all the peripherals.

The MCLK (or XTI) must be used as system clock (sys_clk) before setting the PLL to

standby.

Table 12. Example configurations for power-down

Register bit

Address

Value

Description

EA_STBY

CB_STBY

0x00 on page 81 0xC0

Set the embedded power amplifier and CMOS

bridge to power-down

CLK_FFX_ON 0xC7 on page 134 0x0C

Turn off the FFX modulator clock

ADC_STBY

0xC6 on page 133 0x09

Set the ADC into standby mode

CLK_ADC_ON 0xC6

CLK_PROC_ON 0xC7

0x80

0x08

Turn the ADC clock off

Turn the processing clock off

CLK_SRC_ON 0xC7

0x00

Turn the sample rate converter clock to off

PLL_BYP_UNL 0xC4 on page 132 0x80

Bypass the PLL clock and use MCLK (or XTI) as

source clock when the PLL is not locked (a

safety operational mode)

PLL_PWDN

0xC4

0xA0

CLK_CORE_ON 0xC8 on page 135 0x00

Put the PLL in standby

Turning off the core clock

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Doc ID 15351 Rev 3

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