STA321TR View Datasheet(PDF) - STMicroelectronics
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Description
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STA321TR Datasheet PDF : 157 Pages
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Clock management
Table 15. Clock characteristics
Symbol
Parameter
fMCLK_Range Input clock frequency range
DutyMCLK
Input clock duty cycle
tMCLK_RF
Input clock rise/fall time
fXTI_Range
Input clock frequency range
DutyXTI
Input clock duty cycle
tXTI_RF
Input clock rise/fall time
fBICLK1_Range Input clock frequency range
DutyBICLK1 Input clock duty cycle
tBICLK1_RF
Input clock rise/fall time
fCLKOUT_Range Output clock frequency range
STA321
Min Typ Max Unit
2.048 -
40
-
-
-
2.048 -
40
-
-
-
2.048 -
40
-
-
-
-
-
49.152 MHz
60
%
0.2 ns
49.152 MHz
60
%
0.2 ns
49.152 MHz
60
%
0.2 ns
49.152 MHz
5.1
5.1.1
System clock
Figure 11 above shows the STA321 clock management scheme with all the major clocks. As
can be seen, the system clock (sys_clk) is selected from one of three sources by using
register PLLB on page 136:
z an external clock BICLKI1
z (default) an external clock XTI or MCLK (the unused one must, however, be set to 0)
z the internal PLL.
If the PLL is used there are some design constraints:
z pll_clk_in_i must be in the range: 2.048 MHz to 49.152 MHz
z pll_clk_out must be in the range: 65.536 MHz to 98.304 MHz.
The sys_clk is routed to the peripherals through the clock manager section.
Configuration example
This is an example of the PLL register setup. It is assumed that every peripheral is already
configured and working correctly.
There are other configuration examples to help you get started please refer to other
chapters and also to Chapter 14: Register description on page 77 in order to get all the
necessary and complementary details.
Starting with MCLK as system clock switching to PLL as source
Table 16. Register setup to provide sys_clk from MCLK to PLL
Register Address Value
Description
PLLPFE
PLLB
0xC4
0xC9
0x80
0x00
Safety operational mode: automatic use of MCLK (or XTI)
as system clock if the PLL is not locked
Remove the PLL bypass and use its clock as system
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Doc ID 15351 Rev 3
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