STA321 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA321 Datasheet PDF : 157 Pages
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STA321
Figure 15. SAI_out data multiplexer
P2SDATA[5:3]
ADC (L/R)
16 000
SAI_in1 (L/R) 32 001
SAI_in2 (L/R) 32 010
SRC1 (L/R)
24 011
SRC2 (L/R)
24 100
PROC (ch0/ch1) 24 101
PROC (ch2/ch3) 24 else
SAI_out1
ADC (L/R)
16 000
SAI_in1 (L/R) 32 001
SAI_in2 (L/R) 32 010
SRC1 (L/R)
24 011
SRC2 (L/R)
24 100
PROC (ch0/ch1) 24 101
PROC (ch2/ch3) 24 else
SAI_out2
P2SDATA[2:0]
Digital processing stage
2-channel signal
1-channel signal
6.2
Sampling rate converter
The sample rate converter (SRC) re samples the input data source in order to send to the
processing block an audio stream always with a fixed frequency:
sampling frequency, fS = fsys_clk / 1024 where fsys_clk is the system clock frequency.
In all the examples given here, fS = 96 kHz.
Figure 16. Sample rate converter block diagram
Data input
Interpolation
FIR x2
Interpolation
FIR x2
Threshold
selector
Precomp.
FIR
Sync 6
async.
Data output
LRCK_IN
DRLL
Ratio
The selection between x2 FIR interpolation and direct input data is made automatically by
the threshold selector block. If the input sampling frequency (measured by the DRLL) is
higher than the SRC threshold (that is, more than 81 kHz) the direct connection is selected
(first filter bypassed), otherwise the first x2 filter is added to the data path.
A 3-kHz hysteresis is fixed around the SRC threshold nominal value in order to prevent
unstable oscillations.
Doc ID 15351 Rev 3
35/157
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