STA321MPL View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA321MPL Datasheet PDF : 50 Pages
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Registers
STA321MP
7.2.7
Bit RW RST
Name
Description
4
RW
1
IDE
Invalid input detect mute enable:
1: enable the automatic invalid input detect mute
Setting the IDE bit enables this function, which looks at the input I2S data and will
automatically mute if the signals are perceived as invalid.
Bit RW RST
Name
Description
5
RW
1
BCLE
Binary output mode clock loss detection enable
The BCLE bit detects loss of input MCLK in binary mode and will output 50% duty cycle.
Bit RW RST
Name
Description
6
RW
1
LDTE
LRCLK double trigger protection enable
The LDTE bit actively prevents double triggering of LRCLK.
Bit RW RST
Name
Description
7
RW
1
ECLE
Auto EAPD on clock loss
The ECLE bit controls the device power down signal (EAPD) on clock loss detection. This
function is enabled by default. It is strongly recommended to avoid spurious noise during the
on-off sequence. The STA321MP has the ECLE bit set to 0.
Configuration register I (0x08)
D7
D6
D5
D4
D3
D2
D1
D0
EAPD
0
PSCE
0
This feature utilizes an ADC on SDI78 that provides power supply ripple information for
correction. Registers PSC1, PSC2, PSC3 are utilized in this mode.
Bit RW RST
Name
0
RW
0
PSCE
Description
Power supply ripple correction enable:
0: normal operation
1: PSCorrect operation
Bit RW RST
Name
7
RW
0
EAPD
Description
External amplifier power down:
0: external power stage power-down active
1: normal operation
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Doc ID 022647 Rev 1
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