STA32813TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STA32813TR

2.1-channel high-efficiency digital audio system

STMicroelectronics 

STA328

Register description

6.6

Configuration register F (addr 0x05)

D7

EAPD

0

D6

PWDN

1

D5

D4

D3

D2

ECLE

Reserved

BCLE

IDE

0

1

1

1

D1

OCFG1

0

D0

OCFG0

0

Table 40. Output configuration selection

Bit R/W RST

Name

Description

1:0 RW 00 OCFG[1:0]

Output configuration selection

00: 2-channel (full-bridge) power, 1-channel DDX® is

default

Table 41. Output configuration selection

OCFG[1:0]

00

Output power configuration

2 channel (full-bridge) power, 1 channel DDX®:

1A/1B ◊ 1A/1B

2A/2B ◊ 2A/2B

2 (half-bridge) and 1 (full-bridge) on-board power:

1A ◊ 1A binary

01

2A ◊ 1B binary

3A/3B ◊ 2A/2B binary

10

Reserved

1 channel mono-parallel:

11

3A ◊ 1A/1B

3B ◊ 2A/2B

Table 42. Invalid input detect mute enable

Bit R/W RST

Name

Description

2

RW 1

IDE

Invalid input detect auto-mute enable:

0: disabled

1: enabled

Setting the IDE bit enables this function, which looks at the input I2S data and clocking and

will automatically mute all outputs if the signals are perceived as invalid.

Table 43. Binary clock loss detection enable

Bit R/W RST

Name

Description

3

RW 1

BCLE

Binary output mode clock loss detection enable

0: disabled

1: enabled

Detects loss of input MCLK in binary mode and will output 50% duty cycle to prevent audible

artifacts when input clocking is lost.

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