STA335BWS
3.5
Power-on sequence
Table 7. Power-on sequence
Electrical specifications
VCC
VDD_Dig
Don’t care
XTI
Reset
Don’t care
TR
TC
I2C
PWDN
Don’t care
CMD0 CMD1 CMD2
Note:
Note:
3.6
3.6.1
Where:
TR = minimum time between XTI master clock stable and Reset removal: 1 ms
TC = minimum time between Reset removal and I2C program, sequence start: 1msec
Clock stable means: fmax - fmin < 1 MHz
No specific VCC and VDD_Dig turn−on sequence is required
Testing
Functional pin status
Table 8. Functional pin status
Pin name Pin # Logic value
IC status
PWRDN 23
0
Low absorption
PWRDN 23
1
Normal operation
TWARN 20
0
From external power stage is indicated a temperature
warning
TWARN 20
1
Normal operation
EAPD
19
0
Low absorption for power stage
All internal regulators are switched off
EAPD
19
1
Normal operation
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