STA335BWS
Register description
6.3.2 DDX compensating pulse size register
6.3.3
Bit R/W RST
Name
Description
2
R/W
1
3
R/W
0
4
R/W
1
5
R/W
0
CSZ0
CSZ1
CSZ2
CSZ3
When OM[1,0] = 11, this register determines the
size of the DDX compensating pulse from 0 clock
ticks to 15 clock periods.
Table 6:
Table 15. Compensating pulse size
CSZ[3:0]
Compensating Pulse Size
0000
0001
…
1111
0 ns (0 tick) compensating pulse size
20 ns (1 tick) clock period compensating pulse size
…
300 ns (15 ticks) clock period compensating pulse size
Over-current warning detect adjustment bypass
Bit R/W RST
Name
Description
7
R/W
1
OCRB
0: Over-Current warning Adjustment enabled
1: Over-Current warning Adjustment disabled
The OCWARN input is used to indicate an over-current warning condition. When OCWARN
is asserted (set to 0), the power control block forces an adjustment to the modulation limit
(default is -3 dB) in an attempt to eliminate the over-current warning condition. Once the
over-current warning volume adjustment is applied, it remains in this state until reset is
applied. The level of adjustment can be changed via the TWOCL (thermal warning/over
current limit) setting which is address 0x37 of the user defined coefficient RAM.
6.4
6.4.1
Configuration register D (addr 0x03)
D7
MME
0
D6
ZDE
1
D5
DRC
0
D4
BQL
0
D3
D2
D1
D0
PSL
DSPB
DEMP
HPB
0
0
0
0
High-pass filter bypass
Bit R/W RST
Name
Description
0
R/W
0
HPB
Setting of one bypasses internal AC coupling digital
high-pass filter
The STA335BWS features an internal digital high-pass filter for the purpose of AC coupling.
The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC
signals can cause speaker damage. When HPB = 0, this filter is enabled.
31/68