STA335BWS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA335BWS Datasheet PDF : 68 Pages
| |||
STA335BWS
Register description
6.6.3 Binary output mode clock loss detection
6.6.4
Bit R/W RST
Name
Description
3
R/W
1
BCLE
Binary output mode clock loss detection enable
Detects loss of input MCLK in binary mode and will output 50% duty cycle.
LRCK double trigger protection
6.6.5
Bit R/W RST
Name
Description
4
R/W
1
LDTE
LRCLK double trigger protection enable
Actively prevents double trigger of LRCLK.
Auto EAPD on clock loss
6.6.6
Bit R/W RST
Name
Description
5
R/W
0
ECLE
Auto EAPD on clock loss
When active, issues a power device power down signal (EAPD) on clock loss detection.
IC power down
6.6.7
Bit R/W RST
Name
Description
7
R/W
1
PWDN
0: IC power down low-power condition
1: IC normal operation
The PWDN register is used to place the IC in a low-power state. When PWDN is written
as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted
to power down the power-stage, then the master clock to all internal hardware expect the
I2C block is gated. This places the IC in a very low power consumption state.
External amplifier power down
Bit R/W RST
Name
Description
7
R/W
0
EAPD
0: External power stage power down active
1: Normal operation
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed on a low-power state (disabled). This
register also controls the DDX4B/EAPD output pin when OCFG = 10.
41/68
Share Link: 