STE2001 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STE2001 Datasheet PDF : 36 Pages
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STE2001
- Display blank (E = D = 0)
- Address counter X[6: 0] = 0 and Y[3 : 0] = 0
- Temperature coefficient (TC[1 : 0] = 0)
- Bias system (BS[2 : 0] = 0)
- VOP = 0
- Power Down (PD = 1)
To clear the RAM content a MEMORY BLANK instruction should be executed.
Power Down (PD = 1)
When at Power Down, all LCD outputs are kept at VSS (display off). Bias generator and VLCD generator are OFF
(VLCDOUToutput is discharged to VSS, and then is possible to disconnect VLCDOUT). The internal Oscillator is in
off state. An external clock can be provided. The RAM contents is not cleared.
Charge Pump Factor
The desired Charge Pump Multiplication Factor can be programmed though the S1 and S0 bits, as follows:
S1
S0
Multiplication Factor
0
0
2X
0
1
3X
1
0
4X
1
1
5X
At Reset the X2 factor is selected.
Bias Levels
To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are generated. The ra-
tios among these levels and VLCD, should be selected according to the MUX ratio (m). They are established to
be (Fig. 14):
VLC
D,
n-----+-----3--
n+4
VL
C
D
,
n-----+-----2---
n+4
VLCD
,
-----2--------
n+4
VL
C
D
,
-----1--------
n+4
V L C D ,V S S
Figure 13. Bias level Generator
R
VLCD
n+3
n + 4 ·VLCD
R
n+2
n + 4 ·VLCD
nR
2
n + 4 ·VLCD
R
1
n + 4 ·VLCD
R
VSS D00IN1150
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