STFPC320 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STFPC320

Front panel controller/driver with standby power management and real-time clock

STMicroelectronics 

Real-time clock (RTC) operation

6

Real-time clock (RTC) operation

STFPC320

6.1

Real-time clock

The RTC operates as a slave device through the slave address of the STFPC320 on the

serial bus. Access is obtained by implementing a start condition followed by the correct

slave address (Write: 0x52H and Read: 0x53H). The 16 bytes contained in the device can

then be accessed sequentially in the following order:

1. Reserved

2. Seconds register

3. Minutes register

4. Hours register

5. Square wave/day register

6. Date register

7. Century/month register

8. Year register

9. Calibration register

10. Watchdog register

11 - 15. Alarm registers

16. Flags register

6.2

2-wire bus characteristics

The bus is intended for communication between different ICs. It consists of two lines: a

bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must

be connected to a positive supply voltage (typical voltage is 3.3 V) via a pull-up resistor

(typical value is 10 K). The following protocol has been defined:

● Data transfer may be initiated only when the bus is not busy.

● During data transfer, the data line must remain stable whenever the clock line is High.

● Changes in the data line, while the clock line is High, will be interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

● Bus not busy: both data and clock lines remain High.

● Start data transfer: a change in the state of the data line, from high to Low, while the

clock is High, defines the START condition.

● Stop data transfer: a change in the state of the data line, from Low to High, while the

clock is High, defines the STOP condition.

● Data Valid: the state of the data line represents valid data when after a start condition,

the data line is stable for the duration of the high period of the clock signal. The data on

the line may be changed during the Low period of the clock signal. There is one clock

pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop

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