STFPC320 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STFPC320

Front panel controller/driver with standby power management and real-time clock

STMicroelectronics 

STFPC320

Real-time clock (RTC) operation

6.9

Century bits

These two bits will increment in a binary fashion at the turn of the century, and handle all

leap years correctly. See Table 7 below for additional explanation.

Table 7. Century bits

CB1

CB0

Leap Year?

Example (1)

0

0

Yes

2000

0

1

No

2100

1

0

No

2200

1

1

No

2300

1. Leap year occurs every four years (for years evenly divisible by 4), except for years evenly divisible by

100. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year

2100 is not).

6.10

Note:

Oscillator stop detection

If the oscillator fail (OF) bit is internally set to a ‘1’, this indicates that the oscillator has either

stopped, or was stopped for some period of time and can be used to judge the validity of the

clock and date data. This bit will be set to ‘1’ any time the oscillator stops.

In the event the OF bit is found to be set to ‘1’ at any time other than the initial power-up, the

STOP bit (ST) should be written to a ‘1’, then immediately reset to a ‘0’. This will restart the

oscillator.

The following conditions can cause the OF bit to be set:

● The first time power is applied (defaults to a ‘1’ on power-up).

If the OF bit cannot be written to ‘1’ four (4) seconds after the initial power-up, the STOP bit

(ST) should be written to a ‘1’, then immediately reset to a ‘0’.

● The voltage present on Vcc is insufficient to support oscillation.

● The ST bit is set to a ‘1’.

● External interference of the crystal

If the oscillator fail interrupt enable bit (OFIE) is set to a ‘1’, the IRQ_N/SQW pin will also be

activated. The IRQ_N/SQW output is cleared by resetting the OFIE or OF bit to ‘0’ (NOT by

reading the Flag register).

The OF bit will remain set to ‘1’ until written to logic ‘0’. The oscillator must start and have

run for at least 4 seconds before attempting to reset the OF bit to ‘0’. If the trigger event

occurs during the power-down condition, this bit will be set correctly.

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