STLC5412 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STLC5412 Datasheet PDF : 74 Pages
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STLC5412
TIMING CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
MASTER CLOCK
FMCLK
tW MH
tWML
tRM
tFM
Frequency of MCLK
Tolerance
MCLK/XTAL Input Clock Jitter
Clock Pulse Width, MCLK High Level
Clock Pulse Width, MCLK Low Level
Rise Time of MCLK
Fall Time of MCLK
Including Temperature,
Aging, Etc...
External Clock Source
VIH = VCC – 0.5V
VIL = 0.5V
Used as a Logic Input
–100
20
20
DIGITAL INTERFACE
FBCLK Frequency of BCLK
Formats 1, 2 and 3
256
Format 4 and GCI Mode
512
tWBH Clock Pulse Width, BCLK High Level Measured from VIH to VIH
30
tWBL Clock Pulse Width, BCLK Low Level
Measured from VIL to VIL
30
tRB Risae Time of BCLK
Measured from VIL to VIH
tFB Fall Time of BCLK
Measured from VIH to VIL
tSFB Setup Time, FS High or Low to BCLK Low DSI or GCI Slave Mode only 30
tHBF Hold Time, BCLK Low to FS High or Low DSI or GCI Slave Mode only 20
tDBF Delay Time, BCLK High to FS High or Low DSI or GCI Master Mode only –20
tDBD Delay Time, BCLK High to Data Valid Load = 150pF + 2 LSTTLLoads
tDBDZ Delay Time, BCLK High to Data HZ
tDFD Delay Time, FS High to Data Valid
Load = 150pF + 2 LSTTLLoads
tSDB Setup Time, Data Valid to BCLK Low
0
tHBD Hold time, BCLK to Data Invalid
20
tDBT Delay Time, BCLK High to TSR Low Load = 100pF + 2 LSTTLLoads
tDBTZ Delay Time, BCLK Low to TSR HZ
tDFT Delay Tie, FS High to TSR Low
Load = 100pF + 2 LSTTLLoads
D PORT IN CONTINUOUS MODE: 16KBITS/SEC
tSDD Setup Time, DCLK Low to DX High or Low
50
tHDD Hold Time, DCLK Low to DX High or Low
50
tDDD Delay Time,DCLK High to DR High or Low Load = 50pF + 2 LSTTL Loads
MICROWIRE CONTROL INTERFACE
FCCLK Frequency of CCLK
tWCH Clock Pulse Width, CCLK High Level Measured from VIH to VIH
85
tWCL Clock Pulse Width, CCLK Low Level
Measured from VIL to VIL
85
tRC Rise Time of CCLK
Measured from VIL to VIH
tFC Fall Time of CCLK
Measured from VIH to VIL
tSSC Setup Time, CSB Low to CCLK High
60
tHCS Hold Time, CCLK Low to CSB High
10
tWSH Duration of CSB High
200
tSIC Setup Time, CI Valid to CCLK High
25
tHCI Hold Time, CCLK High to CI Invalid
25
tDSO Delay Time, CSB Low to CO Valid
Out First Bit on CO
tDCO Delay Time CCLK Low to CO Valid
Load = 50 pF + 2LSTTL Loads
tDCOZ Delay Time, CCLK Low to CO HZ
tDCI Delay Time,CCLK Low to INTB Low or HZ Load = 80pF + 2LSTTL Loads
Typ.
15.36
Max. Unit
+100
50
10
10
MHz
ppm
ns pk-pk
ns
ns
ns
ns
4095 KHz
6144 KHz
ns
ns
15
ns
15
ns
ns
ns
20
ns
80
ns
50
ns
80
ns
ns
ns
80
ns
50
ns
80
ns
ns
ns
80
ns
5
MHz
ns
ns
15
ns
15
ns
ns
ns
ns
ns
ns
50
ns
50
ns
50
ns
150
ns
63/74
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