STLC5412 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5412

2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE

STMicroelectronics 

STLC5412

MWPS Micro Wire Port Select register (Signifi-

cant in microwire mode only).

(write only)

Default value: Mode A (5410 compatible)

– Writting FFH value select the mode B to ex-

change data onto CI & CO

– Writing 00H value select the mode A (See Mi-

crowire control interface paragraph for more

details Mode A, Mode B).

Note: Soft Reset has no effect on the select

mode.

BAUD DELAY Register (DBAUD)

After reset: 00H

DBAUD7 DBAUD6 DBAUD5 DBAUD4 DBAUD3 DBAUD2 DBAUD1 DBAUD0

8 bits read-only register that provides the round

trip bauds delay (12.5usec step). It is significant in

LT mode only. The register is split in two sections:

DBAUD4..DBAUD0: 5 bits counter of bauds delay

between SFSx and SFSr rising edges (total digi-

tal delay: tdd).

DBAUD7..DBAUD5: 3 bits to store the internal

elastic memory (FIFO) state. The table A shows

the coding of the 3-stages elastic memory (elas-

tic digital delay: edd).

Table A.

FIFO state

baud delay (edd)

000

-1

010

-2

110

0

-2: 2 bauds have to be subtracted from bauds

counter value (DBAUD4..DBAUD0)

-1: 1 baud has to be subtracted to bauds counter

value (DBAUD4..DBAUD0)

0: no correction

All other FIFO states are used during activation

procedure. Once PLL2 is frozen you can be only

in one of the 3 states in table A.

TX RX Clocks Different Register (DTXRX)

After reset: 00H

7

6

5

4

3

2

1

0

8bits read-only register that provides the phase

difference between transmit clock and receive re-

covered clock by PLL2 in steps of 65.1 nsec.

(clock elastic delay: ced). The register is signifi-

cant in LT mode only.

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