STLC5412
Table 8: REGISTER ACCESS MESSAGES
FUNCTION
NOP
RESERVED
OPR
W
OPR
R
CR1
W
CR1
R
CR2
W
CR2
R
CR3
W
CR3
R
CR4
W
CR4
R
CR5
W
CR5
R
CR6
W
CR6
R
CR7
W
CR7
R
TXB1
W
TXB1
R
TXB2
W
TXB2
R
RXB1
W
RXB1
R
RXB2
W
RXB2
R
TXD
W
TXD
R
RXD
W
RXD
R
RESERVED
BYTE 1
AD7/4 AD3/1
0000 000
0001 XXX
0010 000
0010 000
0010 001
0010 001
0010 010
0010 010
0010 011
0010 011
0010 100
0010 100
0010 101
0010 101
0010 110
0010 110
0010 111
0010 111
0011 000
0011 000
0011 001
0011 001
0011 010
0011 010
0011 011
0011 011
0011 100
0011 100
0011 101
0011 101
0011 11X
AD0
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
7
0
0
CIE
0
FF1
0
SFS
0
LB1
0
EB1
0
IO4
0
T15E
0
0
0
0
0
0
0
0
0
0
0
DX5
0
DR5
0
0
BYTE 2
6
5
4
3
0
0
0
0
0
0
0
0
EIE FIE OB1 OB0
0
0
0
0
FF0 CK2 CK1 CK0
0
0
0
0
NTS DMO DEN ETC
0
0
0
0
LB2 LBD DB1 DB2
0
0
0
0
EB2 ED FFIT ESFr
0
0
0
0
IO3 IO2 IO1 D4
0
0
0
0
ACTAUT PUPAUT QM AIS
0
0
0
0
0
0
0
0
0
0
0
0
0 B1X5 B1X4 B1X3
0
0
0
0
0 B2X5 B2X4 B2X3
0
0
0
0
0 B1R5 B1R4 B1R3
0
0
0
0
0 B2R5 B2R4 B2R3
0
0
0
0
DX4 DX3 DX2 DX1
0
0
0
0
DR4 DR3 DR2 DR1
0
0
0
0
0
0
0
0
2
1
0
0
0
0
0C1 0C0
0
0
DDM CMS
0
0
BP1 BP2
0
0
DBD TLB
0
0
CTLIO MOB
0
0
D3
D2
0
0
TFB0 RFS
0
0
LOCK PL2EN
0
0
B1X2 B1X1
0
0
B2X2 B2X1
0
0
B1R2 B1R1
0
0
B2R2 B2R1
0
0
DX0 SX1
0
0
DR0 SR1
0
0
0
0
0
0
0
C2E
0
BEX
0
RR
0
T15D
0
CTC
0
D1
0
LFS
0
DECT
0
B1X0
0
B2X0
0
B1R0
0
B2R0
0
SX0
0
SR0
0
0
Notes:
1. Bit 7 of byte 1 is the first bit clocked into the UID.
2. All configuration registers can be read-back by setting bit 7 of BYTE 1 equal 1
3. RXOH is a Write only register to force RXEOC, RXM4, RXM56, RXACT status register sending. RST reset the device
4. It is recommended not to access all RESERVED adresses. X means 1 or 0
W refers to a write operation.
R refers to a request for read-back.
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