STLC5412 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STLC5412 Datasheet PDF : 74 Pages
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STLC5412
Table 9: READ BACK MESSAGES
FUNCTION
OPR
CR1
CR2
CR3
CR4
CR5
CR6
CR7
TXB1
TXB2
RXB1
RXB2
TXD
RXD
TXM4
TXM56
TXACT
BEC1
BEC2
ECT1
ECT2
TXEOC
IDR
DECTEOC
DBAUD
BYTE 1
AD7/4 AD3/1
0010 000
0010 001
0010 010
0010 011
0010 100
0010 101
0010 110
0010 111
0011 000
0011 001
0011 010
0011 011
0011 100
0011 101
0100 000
0100 001
0100 010
0100 011
0100 100
0100 101
0100 110
0110 EFG
1000 CCC
1011 EFG
1100 000
BYTE 2
AD0 7
6
5
4
3
2
1
1 CIE
EIE
FIE OB1 OB0 0C1 0C0
1
FF1
FF0
CK2 CK1
CK0 DDM CMS
1 SFS NTS DMO DEN ETC BP1 BP2
1
LB1
LB2
LBD
DB1
DB2 DBD TLB
1 EB1 EB2
ED
FFIT ESFr CTLIO MOB
1
I04
I03
I02
I01
D4
D3
D2
1 T1SE ACTUAT PUPAUT QM
AIS TFB0 RFS
1
0
0
0
0
0
LOCK PL2EN
1
0
0
B1X5 B1X4 B1X3 B1X2 B1X1
1
0
0
B2X5 B2X4 B2X3 B2X2 B2X1
1
0
0
B1R5 B1R4 B1R3 B1R2 B1R1
1
0
0
B2R5 B2R4 B2R3 B2R2 B2R1
1 DX5 DX4 DX3 DX2 DX1 DX0 SX1
1 DR5 DR4 DR3 DR2 DR1 DR0 SR1
1
0
M42x M43x M44x M45x M46x
0
1
0
0
0
M51x M61x M52x FEBx
1
0
0
0
0
C4x
C3x
C2x
1
c7
c6
c5
c4
c3
c2
c1
1
c7
c6
c5
c4
c3
c2
c1
1 ECT17 ECT16 ECT15 ECT14 ECT13 ECT12 ECT11
1 ECT27 ECT26 ECT25 ECT24 ECT23 ECT22 ECT21
H XEOC1 XEOC2 XEOC3 XEOC4 XEOC5 XEOC6 XEOC7
C
0
0
0
0
1
0
0
H DEOC1 DEOC2 DEOC3 DEOC4 DEOC5 DEOC6 DEOC7
1 DBAUD7 DBAUD6 DBAUD5 DBAUD4 DBAUD3 DBAUD2 DBAUD1
0
C2E
BEX
RR
T15D
CTC
D1
LFS
DECT
B1X0
B2X0
B1R0
B2R0
SX0
SR0
M48x
FEBx
C1x
c0
c0
ECT10
ECT20
XEOC8
0
DEOC8
DBAUD0
DTXRX
1100
001
1 DTXRX7 DTXRX6 DTXRX5 DTXRX4 DTXRX3 DTXRX2 DTXRX1 DTXRX0
Notes:
1. For all these registers with the exception of TXEOC, bit 0 of BYTE 1 is set to 1 to indicate read-ba ck message.
2. CR5 configuration/status register is listed with status registers.
3. Bit 7 of BYTE 1 is the first clocked out from the UID.
4. M42x is significant in NT mode only
Table 10: SPONTANEOUS OR DRIVEN MESSAGES
FUNCTION
CR5
STATUS
RXM4
RXM56
RXACT
BEC1
BEC2
RXEOC
BYTE 1
AD7/4 AD3/1
0010 101
0011 111
0100 000
0100 001
0100 010
0100 011
0100 100
0101 EFG
AD0
0
0
0
0
0
0
0
H
7
IO4
PWDN
M41R
0
0
c7
c7
REOC1
6
IO3
0
M42R
0
0
c6
c6
REOC2
5
IO2
0
M43R
0
0
c5
c5
REOC3
BYTE 2
4
3
IO1
D4
0 RxFFU
M44R M45R
M51R M61R
0
C4R
c4
c3
c4
c3
REOC4 REOC5
2
D3
RxFFO
M46R
M52R
C3R
c2
c2
REOC6
1
D2
TxF FU
M47R
FEBR
C2R
c1
c1
REOC7
0
D1
TxFFO
M48R
NEBR
C1R
c0
c0
REOC8
Notes:
1. All status registers can be read by setting first the appropriate command. At any status change, an interrupt cycle is issued.
2. In the RXEOC register:
E = ea1
F = ea2
G = ea3
H = d=0/m = 1
3. For all These registers with the exception of RXEOC, bit 0 of BYTE 1 is set to 0 to indicate a s tatus register.
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