STM32F030F4P6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STM32F030F4P6
STMicroelectronics
STM32F030F4P6 Datasheet PDF : 91 Pages
| |||
STM32F030x4/x6/x8/xC
Electrical characteristics
Symbol
Table 50. ADC characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Unit
tCAL(2)(3)
Calibration time
fADC = 14 MHz
-
ADC clock = HSI14
WLATENCY(2)(4)
ADC_DR register write
latency
ADC clock = PCLK/2
tlatr(2)
Trigger conversion
latency
ADC clock = PCLK/4
fADC = fPCLK/2 =
14 MHz
fADC = fPCLK/2
fADC = fPCLK/4 =
12 MHz
fADC = fPCLK/4
5.9
µs
83
1/fADC
1.5 ADC
1.5 ADC
cycles + 2 - cycles + 3
-
fPCLK cycles
fPCLK cycles
-
4.5
-
fPCLK
cycle
-
8.5
-
fPCLK
cycle
0.196
µs
5.5
0.219
1/fPCLK
µs
10.5
1/fPCLK
fADC = fHSI14 = 14 MHz
0.188
-
0.259
µs
JitterADC
ADC jitter on trigger
conversion
fADC = fHSI14
-
1
-
1/fHSI14
tS(2)
Sampling time
fADC = 14 MHz
-
0.107
-
17.1
µs
1.5
-
239.5
1/fADC
tSTAB(2)
Stabilization time
-
14
1/fADC
tCONV(2)
Total conversion time
(including sampling time)
fADC = 14 MHz,
12-bit resolution
12-bit resolution
1
-
18
µs
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on IDDA and 60 µA
on IDD should be taken into account.
2. Guaranteed by design, not tested in production.
3. Specified value includes only ADC timing. It does not include the latency of the register access.
4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.
EqRuAaItNio<nf--A-1--D--:--C-R---×-A----I-CN-----Am---D--T-aC---xS--×---f--o-l-n--r--m(---2--u-N---l-+-a---2---) – RADC
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
DocID024849 Rev 3
67/91
74
Share Link: 