ST7LITE0xY0, ST7LITESxY0
13.3.2 Operating Conditions with Low Voltage Detector (LVD)
TA = -40 to 85°C, unless otherwise specified
Symbol
Parameter
Conditions
Min Typ Max Unit
VIT+(LVD)
Reset release threshold
(VDD rise)
VIT-(LVD)
Reset generation threshold
(VDD fall)
High Threshold
Med. Threshold
Low Threshold
High Threshold
Med. Threshold
Low Threshold
4.00 1) 4.25 4.50
3.40 1) 3.60 3.80
2.65 1) 2.90 3.15
3.80
4.05 4.30 1)
V
3.20 3.40 3.65 1)
2.40 2.70 2.90 1)
Vhys
VtPOR
tg(VDD)
IDD(LVD)
LVD voltage threshold hysteresis
VDD rise time rate 2)
Filtered glitch delay on VDD
LVD/AVD current consumption
VIT+(LVD)-VIT-(LVD)
Not detected by the LVD
200
mV
20
20000 µs/V
150
ns
220
µA
Notes:
1. Not tested in production.
2. Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on and LVD reset.
When the VDD slope is outside these values, the LVD may not ensure a proper reset of the MCU.
13.3.3 Auxiliary Voltage Detector (AVD) Thresholds
TA = -40 to 85°C, unless otherwise specified
Symbol
Parameter
Conditions
VIT+(AVD)
VIT-(AVD)
Vhys
∆VIT-
1=>0 AVDF flag toggle threshold
(VDD rise)
0=>1 AVDF flag toggle threshold
(VDD fall)
AVD voltage threshold hysteresis
Voltage drop between AVD flag set
and LVD reset activation
High Threshold
Med. Threshold
Low Threshold
High Threshold
Med. Threshold
Low Threshold
VIT+(AVD)-VIT-(AVD)
VDD fall
Min Typ Max Unit
4.40 4.70 5.00
3.90 4.10 4.30
3.20 3.40 3.60
V
4.30 4.60 4.90
3.70 3.90 4.10
2.90 3.20 3.40
150
mV
0.45
V
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