ST7PLITES2Y5KU6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST7PLITES2Y5KU6
STMicroelectronics
ST7PLITES2Y5KU6 Datasheet PDF : 124 Pages
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ST7LITE0xY0, ST7LITESxY0
13.3.4 Internal RC Oscillator and PLL
The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte).
Symbol
Parameter
Conditions Min Typ Max
Unit
VDD(RC)
VDD(x4PLL)
VDD(x8PLL)
Internal RC Oscillator operating voltage
x4 PLL operating voltage
x8 PLL operating voltage
tSTARTUP PLL Startup time
2.4
5.5
2.4
3.3
V
3.3
5.5
60
PLL input clock (fPLL)
cycles
The RC oscillator and PLL characteristics are temperature-dependent and are grouped in two tables.
13.3.4.1 Devices with “6” order code suffix (tested for TA = -40 to +85°C) @ VDD = 4.5 to 5.5V
Symbol
Parameter
Conditions
Min
fRC 1)
ACCRC
IDD(RC)
Internal RC oscillator fre- RCCR = FF (reset value), TA=25°C, VDD=5V
quency
RCCR = RCCR02 ),TA=25°C, VDD=5V
Accuracy of Internal RC TA=25°C,VDD=4.5 to 5.5V
-1
oscillator with
TA=-40 to +85°C, VDD=5V
-5
RCCR=RCCR02)
TA=0 to +85°C, VDD=4.5 to 5.5V
-23)
RC oscillator current con-
sumption
TA=25°C,VDD=5V
tsu(RC)
fPLL
tLOCK
tSTAB
ACCPLL
tw(JIT)
JITPLL
IDD(PLL)
RC oscillator setup time
x8 PLL input clock
PLL Lock time5)
PLL Stabilization time5)
TA=25°C,VDD=5V
x8 PLL Accuracy
fRC = 1MHz@TA=25°C, VDD=4.5 to 5.5V
fRC = 1MHz@TA=-40 to +85°C, VDD=5V
PLL jitter period
fRC = 1MHz
PLL jitter (∆fCPU/fCPU)
PLL current consumption TA=25°C
Typ
760
1000
9703)
13)
2
4
0.14)
0.14)
86)
16)
6003)
Max
+1
+2
+23)
102)
Unit
kHz
%
%
%
µA
µs
MHz
ms
ms
%
%
kHz
%
µA
Notes:
1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a
decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.
2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 24
3. Data based on characterization results, not tested in production
4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy
5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 13 on page 25.
6. Guaranteed by design.
85/124
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