NXP Semiconductors
TDA1566
I2C-bus controlled dual channel/single channel ampliļ¬er
Table 23. Characteristics ā¦continued
Refer to test circuit (see Figure 22); VP = 14.4 V; RL = 4 ā¦; ā40 °C < Tamb < +85 °C and ā40 °C < Tj < +150 °C; unless
otherwise speciļ¬ed.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
αcs
channel separation f = 1 kHz to 10 kHz; Rs = 2 kā¦
42
55
-
dB
SVRR
supply voltage
f = 100 Hz to 10 kHz;
45
70
-
dB
rejection ratio
Rs = 2 kā¦; Vripple = 2 V (p-p)
CMRR
common-mode
ampliļ¬er mode;
60
70
-
dB
rejection ratio
Vcm = 0.3 V (p-p); f = 1 kHz to
3 kHz; Rs = 2 kā¦
Vcm(max)(rms) maximum
f = 1 kHz; Vi = 0.5 V (RMS);
-
common-mode
ampliļ¬er mode
voltage (RMS value) f = 1 kHz; Vi = 1.6 V (RMS);
-
line driver mode
-
1
V
-
0.6
V
Vn(o)(RMS)
Gv(amp)
Gv(ld)
Zi(sym)
RMS noise output
voltage
line driver mode; ļ¬lter 20 Hz to
22 kHz; Rs = 2 kā¦
ampliļ¬er mode; ļ¬lter 20 Hz to
22 kHz; Rs = 2 kā¦
mute mode; ļ¬lter 20 Hz to
22 kHz; Rs = 2 kā¦
voltage gain ampliļ¬er (VOUT1+ ā VOUT1ā) /
mode
(VIN1+ ā VIN1ā)
voltage gain line driver (VOUT1+ ā VOUT1ā) /
mode
(VIN1+ ā VIN1ā)
symmetrical input
impedance
C = 470 nF
-
-
-
25
15
[10] 44
20
50
µV
50
70
µV
20
50
µV
26
27
dB
16
17
dB
60
-
kā¦
αmute
Bp
mute attenuation
power bandwidth
f = 1 kHz; Vi = 1 V (RMS)
ā1 dB; C = 2.2 µF
-
[11] -
80
-
dB
20 to
-
Hz
20000
[1] Operation above 16 V with a 2 ⦠or 1 ⦠mode with reactive load can trigger the ampliļ¬er protection. The ampliļ¬er switches off and will
restart after 8 ms resulting in an āaudio holeā.
[2] If the EN pin is connected with VP a series resistance of 10 k⦠is necessary for load dump robustness.
[3] If the EN pin is left unconnected the ampliļ¬er will be switched off.
[4] The mute release is initiated when the SVR voltage increases above 3.5 V typical. Mute release is deļ¬ned as the moment when the
output signal has reached 10 % of the expected amplitude.
[5] Mute release is deļ¬ned as the moment when the output signal has reached 10 % of the expected amplitude (Gv Ć Vi). Full gain is
deļ¬ned as the moment when the output signal has reached 90 % of the expected amplitude (Gv Ć Vi).
[6] Standard I2C-bus spec: maximum LOW level = 0.3 Ć VDD, minimum HIGH level = 0.7 Ć VDD. To comply with 5 V and 3.3 V logic the
maximum LOW level is deļ¬ned with VDD = 5 V and the minimum HIGH level with VDD = 3.3 V.
[7] If the 1 ⦠pin is connected with VP a series resistance of 10 k⦠is necessary for load dump robustness.
[8] Clip detect is not operational for VP < 10 V.
[9] If an open load is detected the ampliļ¬er is switched in line driver mode.
[10] Rs is the total differential source resistance. ā3 dB cut-off frequency is given as
-2---Ļ-----Ć----R-1---i---Ć-----C----i = 2----Ļ-----Ć----2---2-----k---ā¦------Ć--1---4---7---0-----n---F------Ć----0---.--8-- = 19 Hz assuming worst case low input resistance and 20 % spread in Ci.
[11] Power bandwidth can be limited by the ā3 dB cut-off frequency, see Table note 10.
TDA1566_2
Product data sheet
Rev. 02 ā 20 August 2007
Ā© NXP B.V. 2007. All rights reserved.
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