TDA7563PD
I2C bus
6.6
Acknowledge
The transmitter(*) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 29). The receiver(**) the acknowledges has to pull-down (LOW) the SDA
line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock
pulse.
(*) Transmitter
– master (µP) when it writes an address to the TDA7563PD
– slave (TDA7563PD) when the µP reads a data byte from TDA7563PD
(**) Receiver
– slave (TDA7563PD) when the µP writes an address to the TDA7563PD
– master (µP) when it reads a data byte from TDA7563PD
t(s) Figure 27. Data validity on the I2C bus
uc SDA
Prod t(s) SCL
DATA LINE
te c STABLE, DATA
le u VALID
CHANGE
DATA
ALLOWED
D99AU1031
bso Prod Figure 28. Timing diagram on the I2C bus
) - O lete SCL
ct(s bso SDA
du - O START
D99AU1032
I2CBUS
STOP
Pro t(s) Figure 29. Timing acknowledge clock pulse
lete duc SCL
1
2
3
7
bso ProSDA
OObsolete START
MSB
D99AU1033
8
9
ACKNOWLEDGMENT
FROM RECEIVER
21/29