I2C bus
TDA7567PD
8.2.4
Acknowledge
The transmitter puts a resistive high level on the SDA line during the acknowledge clock
pulse (see Figure 18). The receiver the acknowledges has to pull-down (low) the SDA line
during the acknowledge clock pulse, so that the SDA line is stable low during this clock
pulse.
Transmitter:
● master (µP) when it writes an address to the TDA7567PD
● slave (TDA7567PD) when the µP reads a data byte from TDA7567PD
Receiver:
● slave (TDA7567PD) when the µP writes an address to the TDA7567PD
● master (µP) when it reads a data byte from TDA7567PD
Figure 16. Data validity on the I2C bus
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
Figure 17. Timing diagram on the I2C bus
SCL
SDA
START
D99AU1032
Figure 18. Acknowledge on the I2C bus
SCL
1
2
3
7
I2CBUS
STOP
8
9
SDA
START
MSB
D99AU1033
ACKNOWLEDGMENT
FROM RECEIVER
22/30
Doc ID 16903 Rev 1