TS2012FC View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
TS2012FC Datasheet PDF : 31 Pages
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TS2012FC
5
Package information
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 41. Flip-chip package mechanical drawing
2.1 mm
250μm
G1
INL+
500μm
2.1 mm
Die size: 2.1x2.1 mm ± 30µm
Die height (including bumps):
600µm
Bump diameter: 315µm ±50µm
Bump diameter before reflow:
300µm ±10µm
Bump height: 250µm ±40µm
Die height: 350µm ±20µm
Pitch: 500µm ±50µm
Bump Coplanarity: 60µm max
Optional*: Back coating height:
40µm
40 μm*
600 μm
27/31
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