AT80251G2D-3CSUM(2006) View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT80251G2D-3CSUM
(Rev.:2006)

8/16-bit Microcontroller with Serial Communication Interfaces

Atmel Corporation 

Maximum Total IOL for all:Output Pins71 mA

If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test

conditions.

2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports

1, 2, and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change

from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed

0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic.

3. Capacitive loading on Ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address

lines are stabilizing.

4. Typical values are obtained using VDD = 3 V and TA = 25°C. They are not tested and there is not guarantee on these values.

5. The input threshold voltage of SCL and SDA meets the TWI specification, so an input voltage below 0.3·VDD will be recog-

nized as a logic 0 while an input voltage above 0.7·VDD will be recognized as a logic 1.

Figure 29. IDD/IDL Versus XTAL Frequency; VDD = 2.7 to 3.6 V

15

10

5

0

2

4

6

8

10

12

14

16

max Active mode (mA)

typ Active mode (mA)

max Idle mode (mA)

typ Idle mode (mA)

Frequency at XTAL(1) (MHz)

Note: 1.The clock prescaler is not used: FOSC = FXTAL.

IDD, IDL and IPD Test Conditions

Figure 30. IDD Test Condition, Active Mode

VDD

RST

VDD

VDD

IDD

TSC80251G2D

VDD

P0

(NC)

XTAL2

Clock Signal

XTAL1

EA#

VSS

All other pins are unconnected

66 AT/TSC8x251G2D

4135F–8051–11/06

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