AT/TSC8x251G2D
Timings
Table 42. Real-Time Synchronous Wait AC Timings; VDD = 2.7 to 5.5 V, TA = -40 to
85°C
Symbol Parameter
TCLYV
TCLYX
TRLYV
TRLYX
TWLYV
TWLYX
Wait Clock Low to Wait Set-up
Wait Hold after Wait Clock Low
PSEN#/RD# Low to Wait Set-up
Wait Hold after PSEN#/RD# Low
WR# Low to Wait Set-up
Wait Hold after WR# Low
Min
0
2W·TOSC + 5
0
2W·TOSC + 5
0
2W·TOSC + 5
Max
TOSC - 20
(1+2W)·TOSC - 20
TOSC - 20
(1+2W)·TOSC - 20
TOSC - 20
(1+2W)·TOSC - 20
Unit
ns
ns
ns
ns
ns
ns
Waveforms
Figure 14. Real-time Synchronous Wait State: Code Fetch/Data Read
WCLK
ALE
RD#/PSEN#
WAIT#
State 1
TRLYXmax
TRLYXmin
TRLYV
State 2
State 3
TCLYV
TCLYXmin
TCLYXmax
RD#/PSEN# stretched
P0
A7:0
D7:0
stretched
State 1 (next cycle)
A7:0
P2
A15:8
stretched
A15:8
Figure 15. Real-time Synchronous Wait State: Data Write
WCLK
State 1
State 2
ALE
RD#/PSEN#
WAIT#
TWLYXmax
TWLYXmin
TWLYV
TCLYV
P0
A7:0
P2
A15:8
State 3
TCLYXmin
TCLYXmax
WR# stretched
D7:0
State 1 (next cycle)
stretched
stretched
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4135F–8051–11/06