AT80251G2D-3CSUM(2006) View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT80251G2D-3CSUM
(Rev.:2006)
(Rev.:2006)
Atmel Corporation
AT80251G2D-3CSUM Datasheet PDF : 77 Pages
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AT/TSC8x251G2D
Timings
Table 46. Serial Port AC Timing -Shift Register Mode; VDD = 2.7 to 5.5 V, TA = -40 to
85°C
12 MHz
16 MHz
24 MHz(1)
Symbol Parameter
Min Max Min Max Min Max Unit
TXLXL Serial Port Clock Cycle Time
998
749
500
ns
TQVXH
Output Data Setup to Clock Rising
Edge
833
625
417
ns
TXHQX
Output Data hold after Clock Rising
Edge
165
124
82
ns
TXHDX
Input Data Hold after Clock Rising
Edge
0
0
0
ns
TXHDV
Clock Rising Edge to Input Data
Valid
974
732
482
ns
Note: 1. For high speed versions only.
Waveforms
Figure 17. Serial Port Waveforms - Shift Register Mode
TXLXL
TXD
TQVXH
TXHQX
RXD (Out)
0
1
2
3
TXHDV
TXHDX
RXD (In) Valid
Valid
Valid
Valid
4
Valid
5
Valid
6
Valid
Set TI(1)
7
Set RI(1)
Valid
Note: 1. TI and RI are set during S1P1 of the peripheral cycle following the shift of the eight bit.
53
4135F–8051–11/06
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