AT80251G2D-3CSUM(2006) View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT80251G2D-3CSUM
(Rev.:2006)

8/16-bit Microcontroller with Serial Communication Interfaces

Atmel Corporation 

AC Characteristics - SSLC: TWI Interface

Timings

Waveforms

Table 47. TWI Interface AC Timing; VDD = 2.7 to 5.5 V, TA = -40 to 85°C

Symbol Parameter

INPUT

Min

Max

OUTPUT

Min

Max

THD; STA Start condition hold time

14·TCLCL(4)

4.0 μs(1)

TLOW

SCL low time

16·TCLCL(4)

4.7 μs(1)

THIGH

SCL high time

14·TCLCL(4)

4.0 μs(1)

TRC

SCL rise time

TFC

SCL fall time

1 μs

0.3 μs

-(2)

0.3 μs(3)

TSU; DAT1 Data set-up time

250 ns

20·TCLCL(4)- TRD

TSU; DAT2

SDA set-up time (before repeated START

condition)

250 ns

1 μs(1)

TSU; DAT3 SDA set-up time (before STOP condition)

THD; DAT Data hold time

250 ns

0 ns

8·TCLCL(4)

8·TCLCL(4) - TFC

TSU; STA Repeated START set-up time

14·TCLCL(4)

4.7 μs(1)

TSU; STO

TBUF

TRD

TFD

STOP condition set-up time

Bus free time

SDA rise time

SDA fall time

14·TCLCL(4)

14·TCLCL(4)

1 μs

0.3 μs

4.0 μs(1)

4.7 μs(1)

-(2)

0.3 μs(3)

Notes:

1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of

100 kbit/s.

2. Determined by the external bus-line capacitance and the external bus-line pull-up

resistor, this must be < 1 μs.

3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered

out. Maximum capacitance on bus-lines SDA and

SCL = 400 pF.

4. TCLCL = TOSC = one oscillator clock period.

Figure 18. TWI Waveforms

START or Repeated START condition

SDA

(INPUT/OUTPUT)

SCL

(INPUT/OUTPUT)

TRD

TFD

TRC

TFC

THD;STA TLOW THIGH TSU;DAT1 THD;DAT

Repeated START condition

STOP condition

TSU;STA

START condition

TSU;STO

TSU;DAT3

TBUF

0.7 VDD

0.3 VDD

0.7 VDD

0.3 VDD

TSU;DAT2

54 AT/TSC8x251G2D

4135F–8051–11/06

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