Figure 24. EPROM Verifying Waveforms
P1 = A15:8
P3 = A7:0
P2 = D7:0
P0
Address
TAVQV
TAXQX
Data
TELQV
TEHQZ
Mode = 28h, 29h or 2Bh
AC Characteristics - External Clock Drive and Logic Level References
Definition of Symbols
Table 53. External Clock Timing Symbol Definitions
Signals
C
Clock
H
L
X
Conditions
High
Low
No Longer Valid
Timings
Waveforms
Table 54. External Clock AC Timings; VDD = 4.5 to 5.5 V, TA = -40 to +85°C
Symbol
Parameter
Min
Max
FOSC
TCHCX
TCLCX
TCLCH
TCHCL
Oscillator Frequency
High Time
Low Time
Rise Time
Fall Time
24
10
10
3
3
Figure 25. External Clock Waveform
VDD - 0.5 VIH1
0.45 V
VIL
TCHCL
TCLCH
TCLCX
TCLCL
TCHCX
Unit
MHz
ns
ns
ns
ns
Notes:
1. During AC testing, all inputs are driven at VDD -0.5 V for a logic 1 and 0.45 V for a
logic 0.
2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for
a logic 0.
60 AT/TSC8x251G2D
4135F–8051–11/06