ADV7176 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADV7176

Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder

Analog Devices 

ADV7175/ADV7176

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

SR7–SR5

(000)

ZERO SHOULD

BE WRITTEN TO

THESE BITS

SUBADDRESS REGISTER

SR4 SR3 SR2 SR1 SR0

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

••• • •

••• • •

11111

MODE REGISTER 0

MODE REGISTER 1

SUB CARRIER FREQ REGISTER 0

SUB CARRIER FREQ REGISTER 1

SUB CARRIER FREQ REGISTER 2

SUB CARRIER FREQ REGISTER 3

SUB CARRIER PHASE REGISTER

TIMING MODE REGISTER 0

CLOSED CAPTIONING EXTENDED DATA – BYTE 0

CLOSED CAPTIONING EXTENDED DATA – BYTE 1

CLOSED CAPTIONING DATA – BYTE 0

CLOSED CAPTIONING DATA – BYTE 1

TIMING MODE REGISTER 1

MODE REGISTER 2

NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)

NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)

NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)

NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)

MODE REGISTER 3

MACROVISION REGISTERS (ADV7175 ONLY)

"

"

"

"

"

"

MACROVISION REGISTERS (ADV7175 ONLY)

Figure 30. Subaddress Register

REGISTER ACCESSES

The MPU can write to or read from all of the registers of the

ADV7175/ADV7176 except the subaddress register which is a

write only register. The subaddress register determines which

register the next read or write operation accesses. All communi-

cations with the part through the bus start with an access to the

subaddress register. Then a read/write operation is performed

from/to the target address which then increments to the next

address until a stop command on the bus is performed.

REGISTER PROGRAMMING

The following section describes each register, including

subaddress register, mode registers, subcarrier frequency regis-

ters, subcarrier phase register, timing registers, closed captioning

extended data registers, closed captioning data registers and

NTSC pedestal control registers in terms of its configuration.

Subaddress Register (SR7–SR0)

The communications register is an eight bit write-only register.

After the part has been accessed over the bus and a read/write

operation is selected, the subaddress set up. The subaddress

register determines to/from which register the operation takes

place.

Figure 30 shows the various operations under the control of the

subaddress register. Zero should always be written to SR7–

SR5.

Register Select (SR4–SR0):

These bits are setup to point to the required starting address.

MODE REGISTER 0 MR0 (MR07–MR00)

(Address (SR4–SR0) = 00H)

Mode Register 0 is a 8-bit wide register.

Figure 31 shows the various operations under the control of

Mode Register 0. This register can be read from as well written to.

MR07

MR06

MR05

MR04

MR03

MR02

MR01

MR00

OUTPUT SELECT

MR06

0 YC OUTPUT

1 RGB/YUV OUTPUT

FILTER SELECT

MR04 MR03

0 0 LOW PASS FILTER (A)

0 1 NOTCH FILTER

1 0 EXTENDED MODE

1 1 LOW PASS FILTER (B)

OUTPUT VIDEO

STANDARD SELECTION

MR01 MR00

0

0

NTSC

0

1

PAL (B, D, G, H, I)

1

0

PAL (M)

1

1

RESERVED

MR07

(0)

ZERO SHOULD

BE WRITTEN TO

THIS BIT

RGB SYNC

MR05

0 DISABLE

1 ENABLE

PEDESTAL CONTROL

MR02

0 PEDESTAL OFF

1 PEDESTAL ON

Figure 31. Mode Register 0

REV. A

–17–

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