ADV7176 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADV7176 Datasheet PDF : 36 Pages
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ADV7175/ADV7176
SUBCARRIER FREQUENCY REGISTERS 3–0 (FSC3–FSC0)
(Address (SR4–SR0) = 05H–02H)
These 8-bit wide registers are used to set up the subcarrier fre-
quency. The value of these registers are calculated by using the
following equation:
232 –1
Subcarrier Frequency Register = FCLK * FSCF
i.e.: NTSC Mode, FCLK = 27 MHz, FSCF = 3.5796 MHz
Subcarrier Frequency Register =
232 – 1
27 × 106
* 3.579545
× 106
Subcarrier Frequency Register = 21F07C16 HEX
Figure 33 shows how the frequency is set up by the 4 registers.
SUBCARRIER
FREQUENCY
REG 0
SUBCARRIER
FREQUENCY
REG 1
SUBCARRIER
FREQUENCY
REG 2
SUBCARRIER
FREQUENCY
REG 3
FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8
FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0
Figure 33. Subcarrier Frequency Register
SUBCARRIER PHASE REGISTER (FP7–FP0):
(Address (SR4–SR0) = 06H)
This 8-bit wide register is used to set up the subcarrier phase.
Each bit represents 1.41°.
TIMING REGISTER 0 (TR07–TR00)
(Address (SR4-SR0) = 07H)
Timing Register 0 is a 8-bit wide register.
Figure 34 shows the various operations under the control of
Timing Register 0. This register can be read from as well
written to.
TIMING REGISTER 0 (TR07–TR00)
BIT DESCRIPTION
Master/Slave Control (TR00)
This bit controls whether the ADV7175/ADV7176 is in master
or slave mode.
Timing Mode Control (TR02–TR01)
These bits control the timing mode of the ADV7175/ADV7176
These modes are described in the Timing and Control section
of the data sheet.
BLANK Control (TR03)
This bit controls whether the BLANK input is used when the
part is in slave mode.
Luma Delay Control (TR05–TR04)
These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
Pixel Port Select (TR06)
This bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected the data will be set up on
Pins P7–P0.
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the inter-
nal timing counters. This bit should be toggled after setting up a
new timing mode.
TR07
TR06
TR05
TR04
TR03
TR02
TR01
TR00
TIMING
REGISTER RESET
TR07
PIXEL PORT
CONTROL
TR06
0 8-BIT
1 16-BIT
BLACK INPUT
CONTROL
TR03
0 ENABLE
1 DISABLE
MASTER/SLAVE
CONTROL
TR00
0 SLAVE TIMING
1 MASTER TIMING
LUMA DELAY
TR05 TR04
0
0
0ns DELAY
0
1
74ns DELAY
1
0
148ns DELAY
1
1
222ns DELAY
TIMING MODE
SELECTION
TR02 TR01
0
0 MODE 0
0
1 MODE 1
1
0 MODE 2
1
1 MODE 3
Figure 34. Timing Register 0
REV. A
–19–
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