XE8802MI000 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
Manufacturer
XE8802MI000
Semtech Corporation
XE8802MI000 Datasheet PDF : 193 Pages
| |||
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
4.1 Memory organisation
The XE8802 CPU is built with Harvard architecture. Harvard architecture uses separate instruction and data
memories. The instruction bus and data bus are also separated. The advantage of such a structure is that the CPU
can get a new instruction and read/write data simultaneously. The circuit configuration is shown in Figure 4-1. The
CPU has its 16 internal registers. The instruction memory has a capacity of 8192 22-bit instructions if the pin
NFASTREAD=1. The instruction memory has a capacity of 4096 22-bit instructions if the pin NFASTREAD=0. The
data memory space has 8 low power registers, the peripheral register space, 1024 bytes of RAM and the LCD
control register space.
µF0hµ1FFFF
Instruction
memory
capacity:
8k x 22bit
NFASTREAD=1
4k x 22bit
NFASTREAD=0
CPU
r0
r1
r2
r3
i0h
i0l
i1h
i1l
i2h
i2l
i3h
i3l
iph
ipl
stat
a
0h8022
LCD registers
0h8000
0h047F
RAM
capacity:
1024 bytes
0h0080
0h007F
Peripheral
registers
0h0008
Low power
RAM
0h0000
Figure 4-1. Memory mapping
The CPU internal registers are described in the CPU chapter. A short reference of the low power registers and
peripheral registers is given in 4.3.
4.2 Instruction memory and NFASTREAD
As indicated in chapter 4.1, the instruction memory can be organized in two ways: 4096 instructions with a speed
of 4 to 6 MIPS or 8192 instructions with a speed of 2 to 3 MIPS (see XE8802 performance chapter for more
details).
Important Note:
When programming the device, the correct NFASTREAD option has to be selected in the programmer.
Failure to do so may result in non-functional software. The default option in the programme is
NFASTREAD=1, i.e. the 8k instruction slower operation mode.
© Semtech 2006
www.semtech.com
4-2
Share Link: 