XE8802MI000 View Datasheet(PDF) - Semtech Corporation

Part Name

Description

Manufacturer

XE8802MI000

Sensing Machine Data Acquisition SoC with 16+10 bit ZoomingADC™ Embedded RISC controller and LCD driver

Semtech Corporation 

XE8802 Sensing Machine Data Acquisition MCU

with ZoomingADC™ and LCD driver

Another reset source is the bit Sleep in the RegSysReset register. This source is fully controlled by software and is

only used during the sleep mode.

Four internal reset signals are generated from these sources and distributed through the system:

• nresetcold: is asserted on POR or by the NRESET pin

• nresetglobal: is asserted when nresetcold or any other enabled reset source is active

• nresetsleep: is asserted when the circuit is in sleep mode

• nresetpconf: is asserted when nresetglobal is active and if the EnResetPConf bit in the RegSysCtrl

register is set. This reset is generally used in the different ports. It allows to maintain the port configuration

unchanged while the rest of the circuit is reset.

Table 6-5 shows a summary of the dependency of the internal reset signals on the various reset sources.

In all the tables describing the different registers, the reset source is indicated.

Asserted

reset source

POR

NRESET pin

PortA input

Watchdog

BusError

Sleep

nresetglobal

Asserted

Asserted

Asserted

Asserted

Asserted

-

Internal reset signals

nresetpconf

when

when

EnResetPConf EnRestPConf

is set to 0

is set to 1

Asserted

Asserted

Asserted

Asserted

-

Asserted

-

Asserted

-

Asserted

-

-

nresetsleep

Asserted

Asserted

-

-

-

Asserted

nresetcold

Asserted

Asserted

-

-

-

-

Table 6-5. Internal reset assertion as a function of the reset source.

6.5 Reset source description

6.5.1

Power On Reset

The power on reset (POR) monitors the external supply voltage. It activates a reset on a rising edge of this supply

voltage. The reset is inactivated only if the internal voltage regulator has started up. The POR block performs no

precise voltage level detection.

6.5.2

NRESET pin

Applying a low input state on the NRESET pin can activate the reset.

6.5.3

Programmable Port A input combination

Port A (if present in the product) can generate a reset signal. See the description of the Port A for further

information.

6.5.4

Watchdog reset

The Watchdog will generate a reset if the EnResetWD bit in the RegSysCtrl register has been set and if the

watchdog is not cleared in time by the processor. See chapter 6.8 describing the watchdog for further information.

© Semtech 2006

www.semtech.com

6-4

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