XE8802MI000 View Datasheet(PDF) - Semtech Corporation

Part Name

Description

Manufacturer

XE8802MI000

Sensing Machine Data Acquisition SoC with 16+10 bit ZoomingADC™ Embedded RISC controller and LCD driver

Semtech Corporation 

XE8802 Sensing Machine Data Acquisition MCU

with ZoomingADC™ and LCD driver

In assembler code, the sequence to clear the watchdog is:

move AddrRegSysWd, #0x0A

move AddrRegSysWd, #0x03

Only writing Hx0A followed by Hx03 resets the WD. If some other write instruction is done to the RegSysWd

between the writing of the Hx0A and Hx03 values, the watchdog timer will not be cleared.

It is possible to read the status of the watchdog in the RegSysWd register. The watchdog is a 4 bit counter with a

count range between 0 and 7. The system reset is generated when the counter is reaching the value 8.

6.9 Start-up and watchdog specifications

At start-up of the circuit, the POR block generates a reset signal during tPOR. The circuit starts software execution

after this period (see system chapter). The POR is intended to force the circuit into a correct state at start-up. For

precise monitoring of the supply voltage, the voltage level detector (VLD) has to be used.

Symbol

Parameter

TPOR POR reset duration

Vbat_sl Supply ramp up

Min Typ Max Unit

5

20

ms

0.5

V/ms

Comments

1

WDtime Watchdog timeout period

2

s

2

Table 6. Electrical and timing specifications

Note: 1) The Vbat_sl defines the minimum slope required on VBAT. Correct start-up of the circuit is not guaranteed

if this slope is too slow. In such a case, a delay has to be built using the NRESET pin.

Note: 2) The minimal watchdog timeout period is guaranteed when the internal oscillators are used. In case an

external clock source is used, the watchdog timeout period will be correct in so far the contents of the

RegSysRCTrim1 and RegSysRCTrim2 registers are correct (see clock block documentation for more details).

© Semtech 2006

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