XE8806A/XE8807A
Pos. RegSysCtrl
7 SleepEn
6 EnResetPConf
5 EnBusError
4 EnResetWD
3–0 -
Rw Reset
r w 0 nresetcold
r w 0 nresetcold
r w 0 nresetcold
r w 0 nresetcold
r
0000
Function
enables Sleep mode
0: sleep mode is disabled
1: sleep mode is enabled
enables the nresetpconf signal when the
nresetglobal is active
0: nresetpconf is disabled
1: nresetpconf is enabled
enables reset from BusError
0: BusError reset source is disabled
1: BusError reset source is enabled
enables reset from Watchdog
0: Watchdog reset source is disabled
1: Watchdog reset source is enabled
this bit can not be set to 0 by SW
unused
Table 6-2. RegSysCtrl register.
Pos.
7
6
5
4
3
2–0
RegSysReset
Sleep
SleepFlag
ResetBusError
ResetWD
ResetfromportA
Rw Reset
Function
rw 0 nresetglobal Sleep mode control (reads always 0)
r c 0 nresetcold Sleep mode was active before
r c 0 nresetcold reset source was BusError
r c 0 nresetcold reset source was Watchdog
r c 0 nresetcold reset source was Port A combination
r
000
unused
Table 6-3. RegSysReset register
Pos.
7-4
3
2
1
0
RegSysWd
-
WDKey[3]
WDCounter[3]
WDKey[2]
WDCounter[2]
WDKey[1]
WDCounter[1]
WDKey[0]
WDCounter[0]
Rw Reset
Function
r
0000
unused
w 0 nresetglobal Watchdog Key bit 3
r
Watchdog counter bit 3
w
r
0 nresetglobal Watchdog Key bit 2
Watchdog counter bit 2
w 0 nresetglobal Watchdog Key bit 1
r
Watchdog counter bit 1
w
r
0 nresetglobal
Watchdog Key bit 0
Watchdog counter bit 0
Table 6-4. RegSysWd register
6.4 Reset handling capabilities
There are 5 reset sources:
• Power On Reset (POR)
• External reset from the NRESET pin
• Programmable port A input combination
• Programmable watchdog timer reset
• Programmable BusError reset on processor access outside the allocated memory map
© Semtech 2006
www.semtech.com
6-3