XRT75L03DIV View Datasheet(PDF) - Exar Corporation

Part Name

Description

Manufacturer

XRT75L03DIV

THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

Exar Corporation 

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XRT75L03D

THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0

TABLE 15: XRT75L03D REGISTER MAP - QUICK LOOK

ADDRESS

LOCATION

REGISTER NAME

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0x00

APS/Redundancy Reserved RxON Ch 2 RxON Ch 1 RxON Ch 0 Reserved TxON Ch 2 TxON Ch 1 TxON Ch 0

Control Register

CHANNEL 0 REGISTERS

0x01

Source Level

Interrupt Enable

Register - Ch 0

Reserved

Change of

FL Alarm

Condition

Interrupt

Enable

Change of

RLOL

Condition

Interrupt

Enable

Change of

RLOS

Defect

Condition

Interrupt

Enable

Change of

DMO

Condition

Interrupt

Enable

0x02

Source Level

Interrupt Status

Register - Ch 0

Reserved

Change of

FL Alarm

Condition

Interrupt

Status

Change of

RLOL

Condition

Interrupt

Status

Change of

RLOS

Condition

Interrupt

Status

Change of

DMO

Condition

Interrupt

Status

0x03

Alarm Status

Register - Ch 0

Reserved Loss of

PRBS

Pattern Sync

DLOS

Defect

Declared

ALOS

Defect

Declared

FL Alarm

Declared

RLOL

Condition

Declared

RLOS

Defect

Condition

DMO

Condition

Status

0x04

Transmit Control

Register - Ch 0

Reserved

Internal

Transmit

Drive

Monitoring

Insert

PRBS

Error

Unused

TAOS TxCLK INV TxLEV

0x05

Receive Control

Register - Ch 0

Reserved

DisableD- DisableA-

LOS LOS Detec-

Detector

tor

RxCLK

INV

LOSMUTEn-

able

Receive

Monitor

Mode

Enable

Receive

Equalizer

Enable

0x06

Channel Control

Register - Ch 0

Reserved

PRBS

RLB

Enable

LLB

E3 Mode STS-1/DS3 SR/DR

Mode

Mode

0x07

Jitter Attenuator

Control Register -

Ch 0

Reserved

SONET

APS

Recovery

Time Mode

Disable

JA

RESET

JA1

(JA Mode

Select Bit 1)

JA in

TxPath

JA0

(JA Mode

Select 0)

CHANNEL 1 REGISTERS

0x08

Reserved

Reserved Reserved Reserved Reserved Reserved Reserved

0x09

Source Level

Interrupt Enable

Register - Ch 0

Reserved

Change of

FL Alarm

Condition

Interrupt

Enable

Change of

RLOL

Condition

Interrupt

Enable

Change of

RLOS

Defect

Condition

Interrupt

Enable

Change of

DMO

Condition

Interrupt

Enable

0x0A

Source Level

Interrupt Status

Register - Ch 0

Reserved

Change of

FL Alarm

Condition

Interrupt

Status

Change of

RLOL

Condition

Interrupt

Status

Change of

RLOS

Condition

Interrupt

Status

Change of

DMO

Condition

Interrupt

Status

54

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