XRT75L03DIV View Datasheet(PDF) - Exar Corporation

Part Name

Description

Manufacturer

XRT75L03DIV

THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

Exar Corporation 

XRT75L03D

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REV. 1.0.0 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

BIT NUMBER

NAME

3

FL Alarm Declared

2

Receive LOL Con-

dition Declared

TYPE

R/O

R/O

DEFAULT

VALUE

DESCRIPTION

0

FL (FIFO Limit) Alarm Declared:

This READ-ONLY bit-field indicates whether or not the Jit-

ter Attenuator block (within Channel_n) is currently declar-

ing the FIFO Limit Alarm.

The Jitter Attenuator block will declare the FIFO Limit

Alarm anytime the Jitter Attenuator FIFO comes within two

bit-periods of either overflowing or under-running.

Conversely, the Jitter Attenuator block will clear the FIFO

Limit Alarm anytime the Jitter Attenuator FIFO is NO

longer within two bit-periods of either overflowing or under-

running.

Typically, this Alarm will only be declared whenever there is

a very serious problem with timing or jitter in the system.

0 - Indicates that the Jitter Attenuator block (within

Channel_n) is NOT currently declaring the FIFO Limit

Alarm condition.

1 - Indicates that the Jitter Attenuator block (within

Channel_n) is currently declaring the FIFO Limit Alarm

condition.

NOTE: This bit-field is only active if the Jitter Attenuator

(within Channel_n) has been enabled.

0

Receive LOL (Loss of Lock) Condition Declared:

This READ-ONLY bit-field indicates whether or not the

Receive Section (within Channel_n) is currently declaring

the LOL (Loss of Lock) condition.

The Receive Section (of Channel_n) will declare the LOL

Condition, if any one of the following conditions are met.

• If the frequency of the Recovered Clock signal differs

from that of the signal provided to the E3CLK input (for

E3 applications), the DS3CLK input (for DS3

applications) or the STS-1CLK input (for STS-1

applications) by 0.5% (or 5000ppm) or more.

• If the frequency of the Recovered Clock signal differs

from the line-rate clock signal (for Channel_n) that has

been generated by the SFM Clock Synthesizer PLL (for

SFM Mode Operation) by 0.5% (or 5000ppm) or more.

0 - Indicates that the Receive Section of Channel_n is NOT

currently declaring the LOL Condition.

1 - Indicates that the Receive Section of Channel_n is cur-

rently declaring the LOL Condition.

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