XRT83SL30IV(2003) View Datasheet(PDF) - Exar Corporation

Part Name

Description

Manufacturer

XRT83SL30IV
(Rev.:2003)

SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

Exar Corporation 

XRT83SL30

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SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.0.4

PRELIMINARY

CLOCK SYNTHESIZER

SIGNAL NAME

MCLKE1

MCLKT1

MCLKOUT

PIN #

13

14

16

TYPE

I

I

O

DESCRIPTION

E1 Master Clock Input

This input signal is an independent 2.048MHz clock for E1 system with

required accuracy of better than ±50ppm and a duty cycle of 40% to 60%.

MCLKE1 is used in the E1 mode. Its function is to provide internal timing for

the PLL clock recovery circuit, transmit pulse shaping, jitter attenuator block,

reference clock during transmit all ones data and timing reference for the

microprocessor in Host Mode operation.

MCLKE1 is also input to a programmable frequency synthesizer that under

the control of the CLKSEL[2:0] inputs can be used to generate a master

clock from an accurate external source. In systems that have only one mas-

ter clock source available (E1 or T1), that clock should be connected to both

MCLKE1 and MCLKT1 inputs for proper operation.

NOTES:

1. See pin descriptions for pins CLKSEL[2:0].

2. Internally pulled “Low” with a 50kΩ resistor.

T1 Master Clock Input

This signal is an independent 1.544MHz clock for T1 systems with required

accuracy of better than ±50ppm and duty cycle of 40% to 60%. MCLKT1

input is used in the T1 mode.

NOTES:

1. See MCLKE1 description for further explanation for the usage of this

pin.

2. Internally pulled “Low” with a 50kΩ resistor.

Synthesized Master Clock Output

This signal is the output of the Master Clock Synthesizer PLL which is at T1

or E1 rate based on the mode of operation.

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