XRT83SL30IV(2003) View Datasheet(PDF) - Exar Corporation

Part Name

Description

Manufacturer

XRT83SL30IV
(Rev.:2003)

SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

Exar Corporation 

XRT83SL30

áç

SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.0.4

PRELIMINARY

CONTROL FUNCTION

RESET

SR/DR

LOOP1

LOOP0

41

I

Hardware Reset (Active "Low")

When this pin is tied “Low” for more than 10µs, the device is put in the reset

state.

Pulling RESET “Low” while the ICT pin is also “Low” will put the chip in fac-

tory test mode. This condition should never happen during normal operation.

NOTE: Internally pulled “High” with a 50kΩ resistor.

28

I

Single-Rail/Dual-Rail Data Format

In Hardware Mode, connect this pin "Low" to select transmit and receive

data format in dual-rail mode. In this mode, HDB3 or B8ZS encoder and

decoder are not available.

Connect this pin "High" to select single-rail data format.

NOTE: Internally pulled "Low" with a 50kΩ resistor.

29

I

Loop-back Control pin 1

30

Loop-back Control pin 0

In Hardware Mode, LOOP[1:0] pins are used to control the Loop-back func-

tions according to the following table:

LOOP1

0

LOOP0

0

MODE

Normal Mode

0

1

Local Loop-Back

1

0

Remote Loop-Back

1

1

Digital Loop-Back

EQC4

SDI

EQC3

SDO

EQC2

SCLK

EQC1

CS

EQC0

INT

NOTE: Internally pulled "Low" with a 50kΩ resistor.

21

I

Equalizer Control Input pin 4

In Hardware Mode, this pin together with EQC[3:0] are used for controlling

the transmit pulse shaping, receive monitoring and also to select T1, E1 or J1

modes of operation. See Table 5 for description of Transmit Equalizer Control

bits.

Serial Data Input

Host Mode, See “Serial Interface” on page 4.

22

I

Equalizer Control Input pin 3

See EQC4/SDI description for further explanation for the usage of this pin.

Serial Data Output

O Host Mode, See “Serial Interface” on page 4.

23

I

Equalizer Control Input pin 2

See EQC4/SDI description for further explanation for the usage of this pin.

Serial Interface Clock Input

Host Mode, See “Serial Interface” on page 4.

24

I

Equalizer Control Input pin 1

See EQC4/SDI description for further explanation for the usage of this pin.

Chip Select Input

Host Mode, See “Serial Interface” on page 4.

25

I

Equalizer Control Input pin 0

See EQC4/SDI description for further explanation for the usage of this pin.

O Interrupt Output

Host Mode, See “Serial Interface” on page 4.

13

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